For arch X64, system will enable the page table in SPI to cover 0-512G
range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't
cover the higher address access above 512G before memory-discovered
callback. This series patches provide the solution to enable paging from
temporary RAM Done.

Jiaxin Wu (3):
  UefiCpuPkg/SecCore: Migrate page table to permanent memory
  UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set
  MdeModulePkg/DxeIpl: Align Page table Level setting with previous
    level.

 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c |  39 ++--
 UefiCpuPkg/CpuMpPei/CpuMpPei.h                   |   1 +
 UefiCpuPkg/CpuMpPei/CpuMpPei.inf                 |   1 +
 UefiCpuPkg/CpuMpPei/CpuPaging.c                  | 228 ++++++++++-------------
 UefiCpuPkg/SecCore/SecCore.inf                   |   1 +
 UefiCpuPkg/SecCore/SecCoreNative.inf             |   1 +
 UefiCpuPkg/SecCore/SecMain.c                     | 164 ++++++++++++++++
 UefiCpuPkg/SecCore/SecMain.h                     |   4 +
 8 files changed, 299 insertions(+), 140 deletions(-)

-- 
2.16.2.windows.1



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