On Wed, Sep 20, 2023 at 15:51:23 +0200, Marcin Juszkiewicz wrote:
> W dniu 20.09.2023 o 14:39, Leif Lindholm pisze:
> > Create a helper function to query whether ID_AA64MFR1_EL1 indicates
> > presence of the Virtualization Host Extensions. This feature is only
> > visible in AARCH64 state.
> >
> > Signed-off-by: Leif Lindholm <quic_llind...@quicinc.com>
> > Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
> > Cc: Sami Mujawar <sami.muja...@arm.com>
> > Cc: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
>
> Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Thanks both.
Merged as 89dad77cfbff.
/
Leif
> GTDT for SBSA Reference Platform will use it for NS EL2 virtual timer:
>
> default:
> Virtual EL2 Timer GSIV : 0x1C
> Virtual EL2 Timer Flags : 0x6
>
> non-vhe cpu:
> Virtual EL2 Timer GSIV : 0x0
> Virtual EL2 Timer Flags : 0x0
>
> > ---
> > ArmPkg/Include/Chipset/AArch64.h | 3 +++
> > ArmPkg/Include/Library/ArmLib.h | 18 ++++++++++++++++++
> > ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 15 +++++++++++++++
> > 3 files changed, 36 insertions(+)
> >
> > diff --git a/ArmPkg/Include/Chipset/AArch64.h
> > b/ArmPkg/Include/Chipset/AArch64.h
> > index 690433f68ec8..2e87917049f9 100644
> > --- a/ArmPkg/Include/Chipset/AArch64.h
> > +++ b/ArmPkg/Include/Chipset/AArch64.h
> > @@ -24,6 +24,9 @@
> > // Coprocessor Trap Register (CPTR)
> > #define AARCH64_CPTR_TFP (1 << 10)
> > +// ID_AA64MMFR1 - AArch64 Memory Model Feature Register 0 definitions
> > +#define AARCH64_MMFR1_VH (0xF << 8)
> > +
> > // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
> > #define AARCH64_PFR0_FP (0xF << 16)
> > #define AARCH64_PFR0_GIC (0xF << 24)
> > diff --git a/ArmPkg/Include/Library/ArmLib.h
> > b/ArmPkg/Include/Library/ArmLib.h
> > index 6c5315d7f45f..0169dbc1092c 100644
> > --- a/ArmPkg/Include/Library/ArmLib.h
> > +++ b/ArmPkg/Include/Library/ArmLib.h
> > @@ -764,6 +764,24 @@ ArmHasCcidx (
> > VOID
> > );
> > +#ifdef MDE_CPU_AARCH64
> > +///
> > +/// AArch64-only ID Register Helper functions
> > +///
> > +
> > +/**
> > + Checks whether the CPU implements the Virtualization Host Extensions.
> > +
> > + @retval TRUE FEAT_VHE is implemented.
> > + @retval FALSE FEAT_VHE is not mplemented.
> > +**/
> > +BOOLEAN
> > +EFIAPI
> > +ArmHasVhe (
> > + VOID
> > + );
> > +#endif // MDE_CPU_AARCH64
> > +
> > #ifdef MDE_CPU_ARM
> > ///
> > /// AArch32-only ID Register Helper functions
> > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> > b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> > index 7ab28e3e05fe..da5755106e62 100644
> > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> > @@ -104,3 +104,18 @@ ArmHasCcidx (
> > Mmfr2 = ArmReadIdAA64Mmfr2 ();
> > return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
> > }
> > +
> > +/**
> > + Checks whether the CPU implements the Virtualization Host Extensions.
> > +
> > + @retval TRUE FEAT_VHE is implemented.
> > + @retval FALSE FEAT_VHE is not mplemented.
> > +**/
> > +BOOLEAN
> > +EFIAPI
> > +ArmHasVhe (
> > + VOID
> > + )
> > +{
> > + return ((ArmReadIdAA64Mmfr1 () & AARCH64_MMFR1_VH) != 0);
> > +}
>
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