Hi Pierre, I apologise for asking this level of rework on a v3, but I would much prefer if we could add these definitions in ArmPkg/Include/Chipset/AArch64.h, add helper functions in AArch64Lib* and declare those in ArmLib.h - and then use those instead of doing the direct ID register accesses in AArch64Cap.c in 5/6.
This follows the pattern that is used in that library already (and that we want to expand on). Regards, Leif On Fri, Nov 10, 2023 at 11:48:05 +0100, Pierre Gondois wrote: > Add ArmReadIdAA64Isar0() to ArmLib along with macros > to read specific register fields. > > Signed-off-by: Pierre Gondois <pierre.gond...@arm.com> > --- > ArmPkg/Include/Library/ArmLib.h | 68 ++++++++++++++++++++++ > ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 6 -- > 2 files changed, 68 insertions(+), 6 deletions(-) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index 6aa8a48f07f3..1edaa8d45962 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -805,6 +805,74 @@ ArmHasEte ( > VOID > ); > > +// > +// Bit shifts for the ID_AA64ISAR0_EL1 register. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U) > +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U) > +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 fields. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 field values. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U) > + > +/** Read AA64Isar0 register. > + > + @return AA64Isar0's register value. > +**/ > +UINTN > +EFIAPI > +ArmReadIdAA64Isar0 ( > + VOID > + ); > + > #endif // MDE_CPU_AARCH64 > > #ifdef MDE_CPU_ARM > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > index 6380a019ddc5..07181d940bdd 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > @@ -50,12 +50,6 @@ ArmReadIdAA64Dfr1 ( > VOID > ); > > -UINTN > -EFIAPI > -ArmReadIdAA64Isar0 ( > - VOID > - ); > - > UINTN > EFIAPI > ArmReadIdAA64Isar1 ( > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111288): https://edk2.groups.io/g/devel/message/111288 Mute This Topic: https://groups.io/mt/102504418/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
