Reviewed-by: Ray Ni <ray...@intel.com> Thanks, Ray > -----Original Message----- > From: Sheng, W <w.sh...@intel.com> > Sent: Tuesday, November 21, 2023 3:03 PM > To: devel@edk2.groups.io > Cc: Dong, Eric <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Laszlo > Ersek <ler...@redhat.com>; Wu, Jiaxin <jiaxin...@intel.com>; Tan, Dun > <dun....@intel.com> > Subject: [PATCH v6 5/6] UefiCpuPkg: Backup and Restore MSR IA32_U_CET in > SMI handler. > > OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2. > If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and > the next assemble code is not ENDBR, it will trigger #CP exception > when set CR4.CET bit. > SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET > before set CR4.CET bit, > And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler. > > Signed-off-by: Sheng Wei <w.sh...@intel.com> > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Laszlo Ersek <ler...@redhat.com> > Cc: Wu Jiaxin <jiaxin...@intel.com> > Cc: Tan Dun <dun....@intel.com> > Reviewed-by: Laszlo Ersek <ler...@redhat.com> > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 15 > +++++++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 15 > +++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > index 1da9afab97..9e1155dee6 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > @@ -202,11 +202,21 @@ ASM_PFX(mPatchCetSupported): > push edx > > push eax > > > > + mov ecx, MSR_IA32_U_CET > > + rdmsr > > + push edx > > + push eax > > + > > mov ecx, MSR_IA32_PL0_SSP > > rdmsr > > push edx > > push eax > > > > + mov ecx, MSR_IA32_U_CET > > + xor eax, eax > > + xor edx, edx > > + wrmsr > > + > > mov ecx, MSR_IA32_S_CET > > mov eax, MSR_IA32_CET_SH_STK_EN > > xor edx, edx > > @@ -276,6 +286,11 @@ CetDone: > pop edx > > wrmsr > > > > + mov ecx, MSR_IA32_U_CET > > + pop eax > > + pop edx > > + wrmsr > > + > > mov ecx, MSR_IA32_S_CET > > pop eax > > pop edx > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > index abf9f1a90a..881d3177f7 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > @@ -217,6 +217,11 @@ ASM_PFX(mPatchCetSupported): > push rdx > > push rax > > > > + mov ecx, MSR_IA32_U_CET > > + rdmsr > > + push rdx > > + push rax > > + > > mov ecx, MSR_IA32_PL0_SSP > > rdmsr > > push rdx > > @@ -227,6 +232,11 @@ ASM_PFX(mPatchCetSupported): > push rdx > > push rax > > > > + mov ecx, MSR_IA32_U_CET > > + xor eax, eax > > + xor edx, edx > > + wrmsr > > + > > mov ecx, MSR_IA32_S_CET > > mov eax, MSR_IA32_CET_SH_STK_EN > > xor edx, edx > > @@ -325,6 +335,11 @@ mCetSupportedAbsAddr: > pop rdx > > wrmsr > > > > + mov ecx, MSR_IA32_U_CET > > + pop rax > > + pop rdx > > + wrmsr > > + > > mov ecx, MSR_IA32_S_CET > > pop rax > > pop rdx > > -- > 2.26.2.windows.1
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