Update the RegisterBase and Clk for the Debug Serial Port (DBG2)
to route it to the IOFPGA UART1 and make the SPCR and DBG2 Serial
Ports exclusive.
Signed-off-by: Himanshu Sharma <himanshu.sha...@arm.com>
---
Change-log:
V2:
- Reverse updating the IRQ ID for DBG2 UART.
- Update the commit message.
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index d04b22d3ef51..85a8cbddeae7 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -4,7 +4,7 @@
# This provides platform specific component descriptions and libraries that
# conform to EFI/Framework standards.
#
-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2018 - 2024, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -136,9 +136,9 @@
gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95
# PL011 Serial Debug UART (DBG2)
-
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000
# SBSA Watchdog
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93
--
2.25.1
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