Manish Regmi wrote:
On 3/3/07, Mitch Bradley <[EMAIL PROTECTED]> wrote:
The OLPC OS does not use the ACPI interface, nor does the OLPC firmware
support it . The OS drivers perform the appropriate power management
operations directly, with full knowledge of the behavior of the hardware
on which they operate. The firmware exports a low-level suspend-to-RAM
function in the form of a subroutine. The OS, after doing whatever
driver work is necessary, calls that subroutine. The firmware then
saves the core state and puts the hardware into a low-power state with
RAM powered in self-refresh mode. Upon a wakeup event, the firmware
restores the core state and returns from the subroutine.
The current size of the firmware suspend/resume code is about 1K. It is
written in assembly language, optimized to do its job as quickly as
possible. We hope to be able to do "micro sleeps" so fast that the user
will not realize that the system is sleeping.
OLPC has special hardware features for retaining the image on the screen
and for performing wireless mesh routing while the main processor is
powered off.
Thank you very much for such a nice explanation.
In the code i saw a lot of "magic" port numbers. Is there any
documentation describing them (esp. ones not found in traditional PC).
The suspend/resume code uses MSR registers that are documented in the
AMD chip specs for the Geode GX and 5536 companion chips. The I/O ports
are either legacy PC ports (for example the interrupt controller and
interval timer) or Geode-specific devices documented by the AMD chip
spec (for example MFGPT and SMBUS registers). The OLPC wiki has
pointers to those AMD chip specs. The base port numbers and addresses
for the Geode devices are established by MSR registers, as follows:
I/O ports:
18b0 SMBUS
1000 GPIO
1800 MFGPT
1880 IRQ mapper
1400 PM
1841 ACPI
1480 AC-97
Memory space:
fd000000 Frame buffer
fe000000 Graphics processor
fe004000 Video processor
fe008000 Display controller
fe01a000 OHCI (USB1)
fe01b000 EHCI (USB2)
efc00000 UOC (USB option controller)
fe00c000 CaFe NAND
fe010000 CaFe SD
fe014000 CaFe Camera
These addresses can be "discovered" by doing PCI configuration reads to
PCI device base address registers or by browing the Open Firmware device
tree.
There are a very small number of registers that the AMD public specs
list as reserved, but the code has to use anyway. AMD told us the
required settings for those registers. There are really very few such
registers. The vast majority of the registers are fully documented in
AMD's public specs.
AMD employees and former employees, particularly Jordan Crouse and Tom
Sylla, have helped us a lot. Even with the extensive documentation, it
requires a lot of time and experience to understand how everything fits
together. Without the extensive handholding that those two people gave
me, I would not have been able to figure it all out. Thanks, Jordan and
Tom!
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