According to OMAP3 TRM access to MMU registers shall be strictly 32-bit aligned. Sometimes non-linefetch aborts are observed while flushing TLB, and this fix is intended to get them extincted.
Signed-off-by: Vladimir Zapolskiy <[email protected]> Cc: Omar Ramirez Luna <[email protected]> --- drivers/staging/tidspbridge/hw/hw_mmu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index c214df9..8a93d55 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -558,5 +558,5 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address, void hw_mmu_tlb_flush_all(const void __iomem *base) { - __raw_writeb(1, base + MMU_GFLUSH); + __raw_writel(1, base + MMU_GFLUSH); } -- 1.7.5.4 _______________________________________________ devel mailing list [email protected] http://driverdev.linuxdriverproject.org/mailman/listinfo/devel
