NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
---
misoclib/com/liteeth/common.py | 1 -
misoclib/com/liteeth/generic/__init__.py | 10 ++++++----
misoclib/mem/litesata/common.py | 11 ++++++-----
misoclib/mem/litesata/frontend/bist.py | 1 -
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/misoclib/com/liteeth/common.py b/misoclib/com/liteeth/common.py
index 1aac1ce..59e958b 100644
--- a/misoclib/com/liteeth/common.py
+++ b/misoclib/com/liteeth/common.py
@@ -2,7 +2,6 @@ import math
from collections import OrderedDict
from migen.fhdl.std import *
-from migen.fhdl.decorators import ModuleDecorator
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
diff --git a/misoclib/com/liteeth/generic/__init__.py
b/misoclib/com/liteeth/generic/__init__.py
index 81dc089..053e50d 100644
--- a/misoclib/com/liteeth/generic/__init__.py
+++ b/misoclib/com/liteeth/generic/__init__.py
@@ -1,3 +1,4 @@
+from migen.fhdl.decorators import ModuleTransformer
from misoclib.com.liteeth.common import *
# Generic classes
@@ -10,15 +11,16 @@ class Port:
return r
# Generic modules
-class BufferizeEndpoints(ModuleDecorator):
- def __init__(self, submodule, *args):
- ModuleDecorator.__init__(self, submodule)
+class BufferizeEndpoints(ModuleTransformer):
+ def __init__(self, *names):
+ self.names = names
+ def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
- if name in args or len(args) == 0:
+ if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):
diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py
index 007d514..2a36377 100644
--- a/misoclib/mem/litesata/common.py
+++ b/misoclib/mem/litesata/common.py
@@ -1,7 +1,7 @@
import math
from migen.fhdl.std import *
-from migen.fhdl.decorators import ModuleDecorator
+from migen.fhdl.decorators import ModuleTransformer
from migen.genlib.resetsync import *
from migen.genlib.fsm import *
from migen.genlib.record import *
@@ -252,15 +252,16 @@ def sectors2dwords(n):
return n*logical_sector_size//4
# Generic modules
-class BufferizeEndpoints(ModuleDecorator):
- def __init__(self, submodule, *args):
- ModuleDecorator.__init__(self, submodule)
+class BufferizeEndpoints(ModuleTransformer):
+ def __init__(self, *names):
+ self.names = names
+ def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
- if name in args or len(args) == 0:
+ if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):
diff --git a/misoclib/mem/litesata/frontend/bist.py
b/misoclib/mem/litesata/frontend/bist.py
index 4277cf1..096dab7 100644
--- a/misoclib/mem/litesata/frontend/bist.py
+++ b/misoclib/mem/litesata/frontend/bist.py
@@ -1,7 +1,6 @@
from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.core.link.scrambler import Scrambler
-from migen.fhdl.decorators import ModuleDecorator
from migen.bank.description import *
class LiteSATABISTGenerator(Module):
--
1.9.1
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