Agreed, I have to find a vendor agnostic way to handle this (à la Grlib, http://gaisler.com/index.php/downloads/leongrlib).
Thanks for your review. Best regards, Alain On Monday, April 20, 2015 10:21 AM, Sébastien Bourdeauducq <[email protected]> wrote: This needs to be done for all platforms and used consistently. Also, the only relevant use case I find for such a thing is generic FMC extensions that can be used with different FPGA vendors. Do we have such things yet? Also, remove the underscore in the filename, and names of variables like IOSTD should not be all uppercase. Sébastien On 04/20/2015 03:19 PM, Alain Péteut wrote: > --- > mibuild/altera/__init__.py | 5 ++- > mibuild/altera/_iostd.py | 91 > ++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 94 insertions(+), 2 deletions(-) > create mode 100644 mibuild/altera/_iostd.py > > diff --git a/mibuild/altera/__init__.py b/mibuild/altera/__init__.py > index 9a08458..ea1f5ad 100644 > --- a/mibuild/altera/__init__.py > +++ b/mibuild/altera/__init__.py > @@ -1,2 +1,3 @@ > -from mibuild.altera.platform import AlteraPlatform > -from mibuild.altera.programmer import USBBlaster > +from mibuild.altera.platform import AlteraPlatform # noqa > +from mibuild.altera.programmer import USBBlaster # noqa > +from mibuild.altera._iostd import IOSTD # noqa > diff --git a/mibuild/altera/_iostd.py b/mibuild/altera/_iostd.py > new file mode 100644 > index 0000000..5978300 > --- /dev/null > +++ b/mibuild/altera/_iostd.py > @@ -0,0 +1,91 @@ > +'''ALTERA I/O-Standards > +''' > +import collections > +from mibuild.generic_platform import IOStandard > + > +__all__ = ['IOSTD'] > + > +_LVTTL = collections.namedtuple( > + 'V', > + 'level1V8 level2V5 level3V0 level3V3')( > + IOStandard('1.8-V'), > + IOStandard('2.5-V'), > + IOStandard('3.0-V LVTTL'), > + IOStandard('3.3-V LVTTL')) > + > +_LVCMOS = collections.namedtuple( > + 'V', > + 'level1V2 level1V5 level1V8 level2V5 level3V0 level3V3')( > + IOStandard('1.3 V'), > + IOStandard('1.5 V'), > + IOStandard('1.8 V'), > + IOStandard('2.5 V'), > + IOStandard('3.0-V LVCMOS'), > + IOStandard('3.3-V LVCMOS')) > + > +_SSTL = collections.namedtuple( > + 'V', > + 'level1V5ClassI level1V5ClassII ' > + 'level1V8ClassI level1V8ClassII ' > + 'level2V0ClassI level2V0ClassII')( > + IOStandard('SSTL-15 Class I'), > + IOStandard('SSTL-15 Class II'), > + IOStandard('SSTL-18 Class I'), > + IOStandard('SSTL-18 Class II'), > + IOStandard('SSTL-2 Class I'), > + IOStandard('SSTL-2 Class II')) > + > +_HSTL = collections.namedtuple( > + 'V', > + 'level1V2ClassI level1V2ClassII level1V5ClassI level1V5ClassII ' > + 'level1V8ClassI level1V8ClassII')( > + IOStandard('1.2-V HSTL Class I'), > + IOStandard('1.2-V HSTL Class II'), > + IOStandard('HSTL Class I'), > + IOStandard('HSTL Class II'), > + IOStandard('1.8-V HSTL Class I'), > + IOStandard('1.8-V HSTL Class II')) > + > +_DiffSSTL = collections.namedtuple( > + 'V', > + 'level1V5 level1V8 level2V0')( > + IOStandard('Differential 1.5-V SSTL'), > + IOStandard('Differential 1.8-V SSTL'), > + IOStandard('Differential SSTL-2')) > + > +_DiffHSTL = collections.namedtuple( > + 'V', > + 'level1V2 level1V5 level1V8')( > + IOStandard('Differential 1.2-V HSTL'), > + IOStandard('Differential 1.5-V HSTL'), > + IOStandard('Differential 1.8-V HSTL')) > + > +_PCML = collections.namedtuple( > + 'V', > + 'level1V2 level1V4 level1V5 level2V5')( > + IOStandard('1.2-V PCML'), > + IOStandard('1.4-V PCML'), > + IOStandard('1.5-V PCML'), > + IOStandard('2.5-V PCML')) > + > +IOSTD = collections.namedtuple( > + 'CONST', > + 'LVTTL LVCMOS PCI PCIX SSTL HSTL DiffSSTL DiffHSTL ' > + 'LVDS RSDS miniLVDS LVPECL DiffLVPECL BLVDS PCML DiffPCML HCSL')( > + _LVTTL, > + _LVCMOS, > + IOStandard('3.0-V PCI'), > + IOStandard('3.0-V PCI-X'), > + _SSTL, > + _HSTL, > + _DiffSSTL, > + _DiffHSTL, > + IOStandard('LVDS'), > + IOStandard('RSDS'), > + IOStandard('mini-LVDS'), > + IOStandard('LVPECL'), > + IOStandard('Differential LVPECL'), > + IOStandard('BLVDS'), > + _PCML, > + IOStandard('Differential PCML'), > + IOStandard('HCSL')) > _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
