On 09/17/2015 07:00 PM, Jeremy Herbert wrote: > I'm trying to make it create three separate verilog modules (top, > AndGate, XorGate) and instantiate the latter two inside the top module. > Does migen support this?
You have to do it manually, i.e. Verilog export and instantiate each module separately. Also, what you are doing is an overly difficult and inefficient way of implementing additions in FPGAs. Just use x.eq(a+b) instead. _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
