>From cee701e872570300eadebf0cbec1b831cb0665eb Mon Sep 17 00:00:00 2001
From: Yann Sionneau <y...@sionneau.net>
Date: Sat, 7 Nov 2015 12:11:29 +0000
Subject: [PATCH 2/2] replace Counter in Converters
---
misoc/interconnect/wishbone.py | 46 +++++++++++++++++++++++++++---------------
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
index d24148b..af53dd3 100644
--- a/misoc/interconnect/wishbone.py
+++ b/misoc/interconnect/wishbone.py
@@ -177,15 +177,22 @@ class DownConverter(Module):
read = Signal()
write = Signal()
- counter = Counter(max=ratio)
- self.submodules += counter
+ counter = Signal(max=ratio)
+ counter_reset = Signal()
+ counter_ce = Signal()
+ self.sync += \
+ If(counter_reset,
+ counter.eq(0)
+ ).Elif(counter_ce,
+ counter.eq(counter + 1)
+ )
counter_done = Signal()
- self.comb += counter_done.eq(counter.value == ratio-1)
+ self.comb += counter_done.eq(counter == ratio-1)
# Main FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
- counter.reset.eq(1),
+ counter_reset.eq(1),
If(master.stb & master.cyc,
If(master.we,
NextState("WRITE")
@@ -201,7 +208,7 @@ class DownConverter(Module):
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
- counter.ce.eq(1),
+ counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
@@ -217,7 +224,7 @@ class DownConverter(Module):
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
- counter.ce.eq(1),
+ counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
@@ -235,7 +242,7 @@ class DownConverter(Module):
).Else(
slave.cti.eq(2)
),
- slave.adr.eq(Cat(counter.value, master.adr))
+ slave.adr.eq(Cat(counter, master.adr))
]
# Datapath
@@ -245,13 +252,13 @@ class DownConverter(Module):
slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]),
slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to])
]
- self.comb += Case(counter.value, cases)
+ self.comb += Case(counter, cases)
cached_data = Signal(dw_from)
self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
self.sync += \
- If(read & counter.ce,
+ If(read & counter_ce,
cached_data.eq(master.dat_r)
)
@@ -291,13 +298,20 @@ class UpConverter(Module):
self.submodules += address
self.comb += address.d.eq(master.adr)
- counter = Counter(max=ratio)
- self.submodules += counter
+ counter = Signal(max=ratio)
+ counter_ce = Signal()
+ counter_reset = Signal()
+ self.sync += \
+ If(counter_reset,
+ counter.eq(0)
+ ).Elif(counter_ce,
+ counter.eq(counter + 1)
+ )
counter_offset = Signal(max=ratio)
counter_done = Signal()
self.comb += [
counter_offset.eq(address.q),
- counter_done.eq((counter.value + counter_offset) == ratio-1)
+ counter_done.eq((counter + counter_offset) == ratio-1)
]
cached_data = Signal(dw_to)
@@ -318,7 +332,7 @@ class UpConverter(Module):
# Main FSM
self.submodules.fsm = fsm = FSM()
fsm.act("IDLE",
- counter.reset.eq(1),
+ counter_reset.eq(1),
If(master.stb & master.cyc,
address.ce.eq(1),
If(master.we,
@@ -335,7 +349,7 @@ class UpConverter(Module):
fsm.act("WRITE",
If(master.stb & master.cyc,
write.eq(1),
- counter.ce.eq(1),
+ counter_ce.eq(1),
master.ack.eq(1),
If(counter_done,
NextState("EVICT")
@@ -388,7 +402,7 @@ class UpConverter(Module):
write_sel = Signal()
cases[i] = write_sel.eq(1)
self.comb += [
- cached_sels[i].reset.eq(counter.reset),
+ cached_sels[i].reset.eq(counter_reset),
If(write,
cached_datas[i].d.eq(master.dat_w),
).Else(
@@ -400,7 +414,7 @@ class UpConverter(Module):
cached_sels[i].ce.eq(1)
)
]
- self.comb += Case(counter.value + counter_offset, cases)
+ self.comb += Case(counter + counter_offset, cases)
cases = {}
for i in range(ratio):
--
1.9.1
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