* move top add_constants() into a Config(Module, AutoCSR)
* also generate *_read() accessors to allow more seamless
switching between CSRConstant/CSRStatus
* adapt runtime (SYSTEM_ -> CONFIG_ etc.)
* these constants can be used from within FHDL as well
(top.config.CLOCK_FREQUENCY is also a FHDL Constant)
---
misoc/integration/config.py | 10 ++++++++++
misoc/integration/cpu_interface.py | 19 ++++++++++++-------
misoc/integration/soc_core.py | 9 +++++++--
misoc/integration/soc_sdram.py | 2 +-
misoc/software/bios/boot.c | 2 +-
misoc/software/bios/main.c | 4 ++--
misoc/software/libbase/spiflash.c | 16 ++++++++--------
misoc/software/libbase/system.c | 4 ++--
misoc/software/libbase/time.c | 2 +-
misoc/software/libnet/microudp.c | 2 +-
misoc/software/memtest/main.c | 6 +++---
misoc/targets/kc705.py | 4 ++--
misoc/targets/pipistrello.py | 4 ++--
13 files changed, 52 insertions(+), 32 deletions(-)
create mode 100644 misoc/integration/config.py
diff --git a/misoc/integration/config.py b/misoc/integration/config.py
new file mode 100644
index 0000000..c04fc4d
--- /dev/null
+++ b/misoc/integration/config.py
@@ -0,0 +1,10 @@
+from migen import *
+
+from misoc.interconnect.csr import AutoCSR, CSRConstant
+
+class Config(Module, AutoCSR):
+ def __setitem__(self, key, value):
+ setattr(self, key, CSRConstant(value, name=key))
+
+ def __getitem__(self, key):
+ return getattr(self, key).value
diff --git a/misoc/integration/cpu_interface.py
b/misoc/integration/cpu_interface.py
index 0514b4e..7bcb526 100644
--- a/misoc/integration/cpu_interface.py
+++ b/misoc/integration/cpu_interface.py
@@ -102,13 +102,18 @@ def get_csr_header(regions, constants,
with_access_functions=True):
r += "\n/* constants */\n"
for name, value in constants:
- r += "#define " + name
- if value is not None:
- if isinstance(value, str):
- r += " \"" + value + "\""
- else:
- r += " " + str(value)
- r += "\n"
+ if value is None:
+ r += "#define "+name+"\n"
+ continue
+ if isinstance(value, str):
+ value = "\"" + value + "\""
+ ctype = "const char *"
+ else:
+ value = str(value)
+ ctype = "int"
+ r += "#define "+name+" "+value+"\n"
+ r += "static inline "+ctype+" "+name.lower()+"_read(void) {\n"
+ r += "\treturn "+value+";\n}\n"
r += "\n#endif\n"
return r
diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py
index cb18b35..c69b71b 100644
--- a/misoc/integration/soc_core.py
+++ b/misoc/integration/soc_core.py
@@ -1,9 +1,11 @@
from operator import itemgetter
+import warnings
from migen import *
from misoc.cores import lm32, mor1kx, identifier, timer, uart
from misoc.interconnect import wishbone, csr_bus, wishbone2csr
+from misoc.integration.config import Config
__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
@@ -70,6 +72,8 @@ class SoCCore(Module):
self._wb_masters = []
self._wb_slaves = []
+ self.submodules.config = Config()
+
if cpu_type == "lm32":
self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
elif cpu_type == "or1k":
@@ -102,7 +106,7 @@ class SoCCore(Module):
if ident:
self.submodules.identifier = identifier.Identifier(ident)
- self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
+ self.config["CLOCK_FREQUENCY"] = int(clk_freq)
if with_timer:
self.submodules.timer0 = timer.Timer()
@@ -154,6 +158,7 @@ class SoCCore(Module):
return self._csr_regions
def add_constant(self, name, value=None):
+ warnings.warn("use CSRConstant and/or Config", DeprecationWarning)
self._constants.append((name, value))
def get_constants(self):
@@ -184,7 +189,7 @@ class SoCCore(Module):
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override,
(self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width,
memory)
for name, constant in self.csrbankarray.constants:
- self.add_constant((name + "_" + constant.name).upper(),
constant.value)
+ self._constants.append(((name + "_" + constant.name).upper(),
constant.value))
# Interrupts
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py
index 88957d3..ca143ec 100644
--- a/misoc/integration/soc_sdram.py
+++ b/misoc/integration/soc_sdram.py
@@ -68,7 +68,7 @@ class SoCSDRAM(SoCCore):
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow
larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024)
if self.l2_size:
- self.add_constant("L2_SIZE", self.l2_size)
+ self.config["L2_SIZE"] = self.l2_size
# add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface()
diff --git a/misoc/software/bios/boot.c b/misoc/software/bios/boot.c
index 635bd64..114da52 100644
--- a/misoc/software/bios/boot.c
+++ b/misoc/software/bios/boot.c
@@ -34,7 +34,7 @@ static int check_ack(void)
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(SYSTEM_CLOCK_FREQUENCY/4);
+ timer0_load_write(CONFIG_CLOCK_FREQUENCY/4);
timer0_en_write(1);
timer0_update_value_write(1);
recognized = 0;
diff --git a/misoc/software/bios/main.c b/misoc/software/bios/main.c
index 76984d1..ad81838 100644
--- a/misoc/software/bios/main.c
+++ b/misoc/software/bios/main.c
@@ -353,7 +353,7 @@ static void do_command(char *c)
else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
else if(strcmp(token, "ident") == 0) ident();
-#ifdef L2_SIZE
+#ifdef CONFIG_L2_SIZE
else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
#endif
@@ -468,7 +468,7 @@ static int test_user_abort(void)
#endif
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(SYSTEM_CLOCK_FREQUENCY*2);
+ timer0_load_write(CONFIG_CLOCK_FREQUENCY*2);
timer0_en_write(1);
timer0_update_value_write(1);
while(timer0_value_read()) {
diff --git a/misoc/software/libbase/spiflash.c
b/misoc/software/libbase/spiflash.c
index 31d56a1..3acdc63 100644
--- a/misoc/software/libbase/spiflash.c
+++ b/misoc/software/libbase/spiflash.c
@@ -1,6 +1,6 @@
#include <generated/csr.h>
-#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
+#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
#include <spiflash.h>
@@ -71,7 +71,7 @@ static void wait_for_device_ready(void)
void erase_flash_sector(unsigned int addr)
{
- unsigned int sector_addr = addr & ~(SPIFLASH_SECTOR_SIZE - 1);
+ unsigned int sector_addr = addr & ~(CONFIG_SPIFLASH_SECTOR_SIZE - 1);
spiflash_bitbang_en_write(1);
@@ -93,8 +93,8 @@ void write_to_flash_page(unsigned int addr, const unsigned
char *c, unsigned int
{
unsigned int i;
- if(len > SPIFLASH_PAGE_SIZE)
- len = SPIFLASH_PAGE_SIZE;
+ if(len > CONFIG_SPIFLASH_PAGE_SIZE)
+ len = CONFIG_SPIFLASH_PAGE_SIZE;
spiflash_bitbang_en_write(1);
@@ -115,14 +115,14 @@ void write_to_flash_page(unsigned int addr, const
unsigned char *c, unsigned int
spiflash_bitbang_en_write(0);
}
-#define SPIFLASH_PAGE_MASK (SPIFLASH_PAGE_SIZE - 1)
+#define SPIFLASH_PAGE_MASK (CONFIG_SPIFLASH_PAGE_SIZE - 1)
void write_to_flash(unsigned int addr, const unsigned char *c, unsigned int
len)
{
unsigned int written = 0;
if(addr & SPIFLASH_PAGE_MASK) {
- written = min(SPIFLASH_PAGE_SIZE - (addr & SPIFLASH_PAGE_MASK), len);
+ written = min(CONFIG_SPIFLASH_PAGE_SIZE - (addr & SPIFLASH_PAGE_MASK),
len);
write_to_flash_page(addr, c, written);
c += written;
addr += written;
@@ -130,7 +130,7 @@ void write_to_flash(unsigned int addr, const unsigned char
*c, unsigned int len)
}
while(len > 0) {
- written = min(len, SPIFLASH_PAGE_SIZE);
+ written = min(len, CONFIG_SPIFLASH_PAGE_SIZE);
write_to_flash_page(addr, c, written);
c += written;
addr += written;
@@ -138,4 +138,4 @@ void write_to_flash(unsigned int addr, const unsigned char
*c, unsigned int len)
}
}
-#endif /* CSR_SPIFLASH_BASE && SPIFLASH_PAGE_SIZE */
+#endif /* CSR_SPIFLASH_BASE && CONFIG_SPIFLASH_PAGE_SIZE */
diff --git a/misoc/software/libbase/system.c b/misoc/software/libbase/system.c
index c973653..0e8ff97 100644
--- a/misoc/software/libbase/system.c
+++ b/misoc/software/libbase/system.c
@@ -67,14 +67,14 @@ void flush_cpu_dcache(void)
#endif
}
-#ifdef L2_SIZE
+#ifdef CONFIG_L2_SIZE
void flush_l2_cache(void)
{
unsigned int i;
register unsigned int addr;
register unsigned int dummy;
- for(i=0;i<2*L2_SIZE/4;i++) {
+ for(i=0;i<2*CONFIG_L2_SIZE/4;i++) {
addr = MAIN_RAM_BASE + i*4;
#if defined (__lm32__)
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
diff --git a/misoc/software/libbase/time.c b/misoc/software/libbase/time.c
index 9f7f1db..2d04d71 100644
--- a/misoc/software/libbase/time.c
+++ b/misoc/software/libbase/time.c
@@ -6,7 +6,7 @@ void time_init(void)
int t;
timer0_en_write(0);
- t = 2*SYSTEM_CLOCK_FREQUENCY;
+ t = 2*CONFIG_CLOCK_FREQUENCY;
timer0_reload_write(t);
timer0_load_write(t);
timer0_en_write(1);
diff --git a/misoc/software/libnet/microudp.c b/misoc/software/libnet/microudp.c
index 1f0191f..5e4ff7b 100644
--- a/misoc/software/libnet/microudp.c
+++ b/misoc/software/libnet/microudp.c
@@ -427,7 +427,7 @@ static void busy_wait(unsigned int ds)
{
timer0_en_write(0);
timer0_reload_write(0);
- timer0_load_write(SYSTEM_CLOCK_FREQUENCY/10*ds);
+ timer0_load_write(CONFIG_CLOCK_FREQUENCY/10*ds);
timer0_en_write(1);
timer0_update_value_write(1);
while(timer0_value_read()) timer0_update_value_write(1);
diff --git a/misoc/software/memtest/main.c b/misoc/software/memtest/main.c
index 66a8a20..9b6facc 100644
--- a/misoc/software/memtest/main.c
+++ b/misoc/software/memtest/main.c
@@ -25,13 +25,13 @@ static void membw_service(void)
unsigned int rdb, wrb;
unsigned int dw;
- if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) {
+ if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) {
sdram_controller_bandwidth_update_write(1);
nr = sdram_controller_bandwidth_nreads_read();
nw = sdram_controller_bandwidth_nwrites_read();
dw = sdram_controller_bandwidth_data_width_read();
- rdb = (nr*SYSTEM_CLOCK_FREQUENCY >> (24 - log2(dw)))/1000000ULL;
- wrb = (nw*SYSTEM_CLOCK_FREQUENCY >> (24 - log2(dw)))/1000000ULL;
+ rdb = (nr*CONFIG_CLOCK_FREQUENCY >> (24 - log2(dw)))/1000000ULL;
+ wrb = (nw*CONFIG_CLOCK_FREQUENCY >> (24 - log2(dw)))/1000000ULL;
printf("read:%5dMbps write:%5dMbps all:%5dMbps\n", rdb, wrb,
rdb + wrb);
}
}
diff --git a/misoc/targets/kc705.py b/misoc/targets/kc705.py
index 1af1ad6..2ff6cad 100755
--- a/misoc/targets/kc705.py
+++ b/misoc/targets/kc705.py
@@ -104,8 +104,8 @@ class BaseSoC(SoCSDRAM):
i_CLK=0, i_GSR=0, i_GTS=0,
i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads,
dummy=11, div=2)
- self.add_constant("SPIFLASH_PAGE_SIZE", 256)
- self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
+ self.config["SPIFLASH_PAGE_SIZE"] = 256
+ self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
diff --git a/misoc/targets/pipistrello.py b/misoc/targets/pipistrello.py
index b78ded2..62dab0d 100755
--- a/misoc/targets/pipistrello.py
+++ b/misoc/targets/pipistrello.py
@@ -125,8 +125,8 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_rom_size:
self.submodules.spiflash =
spi_flash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
- self.add_constant("SPIFLASH_PAGE_SIZE", 256)
- self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
+ self.config["SPIFLASH_PAGE_SIZE"] = 256
+ self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
--
1.9.1
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