Hi sb0, Florent & MiSoC developers,

At the start of the year, TimVideos & Apertus applied with Felix Held to
the German Prototype Fund (https://prototypefund.de/en/). We applied to
fund Felix to work on two things;

 (a) Creating a fully open source SDI (https://en.wikipedia.org/
wiki/Serial_digital_interface) core in Migen+MiSoC / LiteX

 (b) Improving support for Zynq processors in Migen+MiSoC / LiteX

We recently got confirmation that our application has approved! Initially
we are going to concentrate on the SDI problem, but eventually Felix will
want to start looking at the bus interface on the Zynq.

We want eventually enable switching from using a softcore like the lm32 or
mor1k to using a hardcore in something like the Zynq seamlessly, retaining
all the awesome MiSoC features like automatic header generation and similar.

The use case is actually pretty similar to using a MiSoC based design
through LitePCIe bridge. So it definitely makes sense to use that for
inspiration.

Our initial use case will be for streaming video from the FPGA fabric (such
as from the SDI core) into DDR ram connected to the hardcore. This is
because the microZed used by Apertus in the AXIOM doesn't have any DDR
memory attached to the FPGA pins. In the distant future I'm hoping that we
can use MiSoC or LiteX as the basis for the full AXIOM gateware.

Migen+MiSoC currently has good support for the Wishbone bus. We would like
a similar level of support for the bus inside the Zynq IC rather than
needing to use wishbone bridges.

So the primary question is; how should we approach this work? As we
*definitely* want to get this work merged into MiSoC upstream, we would
definitely appreciate your advice.

I've started putting together a Google Doc with my notes + thoughts so far.
You can find it here ->
https://docs.google.com/document/d/1aAJHfHo4-E6SllYoOafiLOIncv0NaQoi8fuC12hMTjg/edit#

Thanks for your help!

Tim 'mithro' Ansell
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