Alright.
How about this then?
But should unsigned constants with negative values be allowed?
Baptiste
________________________________________
From: Sébastien Bourdeauducq [s...@m-labs.hk]
Sent: Monday, December 04, 2017 10:54 AM
To: Baptiste Gouraud; devel@lists.m-labs.hk
Subject: Re: [M-Labs devel] Signal(reset=-1)
Hi,
Signal(reset=-1) is incorrect, since the default range of a signal is
0/1, and does not include -1. The reset value should not affect the
range of the signal.
What can be done instead is preprocess reset values as is they were
assigned to the signal. x.eq(-1) with x a 1-bit unsigned signal is
equivalent to x.eq(1). So Migen should change your -1 reset value to 1.
This should be done in the Verilog backend, as it is possible to rewrite
the reset value of a signal after creation (e.g. sig.reset = 34). And I
believe the Migen simulator already behavior equivalent to what I am
describing.
Sébastien
On Monday, December 04, 2017 05:15 PM, Baptiste Gouraud wrote:
> Dear migen devs,
>
> I came across an unexpected behavior when playing around with migen.
> Not a big thing, see attached patch for description and proposed change.
>
> Thanks everyone for these nice tools you are developing and sharing,
> Baptiste
>
>
> _______________________________________________
> M-Labs devel mailing list
> https://ssl.serverraum.org/lists/listinfo/devel
>
From 2ee8a7e862db0cf9de19d6d20c924d85e7f2a302 Mon Sep 17 00:00:00 2001
From: Baptiste Gouraud <baptiste dot gouraud at unibas dot ch>
Date: Mon, 4 Dec 2017 11:38:45 +0100
Subject: [PATCH] Verilog backend now handling eventual (abusive?) unsigned
constants with a negative value (this would previously lead to a verilog
syntax error).
---
migen/fhdl/verilog.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 9e2bd82..965f4f6 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -47,6 +47,8 @@ def _printconstant(node):
return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
True)
else:
+ while node.value < 0:
+ node.value += 2**node.nbits
return str(node.nbits) + "'d" + str(node.value), False
--
2.7.4
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