Hi,
part of that tutorial and in particular the simulation is out of date.
Please look at recent simulation code in the examples, unittests, artiq,
etc. instead.
Sébastien
On Wednesday, December 13, 2017 10:10 PM, Kustaa Nyholm wrote:
Hi,
I'm trying to work through the example here:
https://m-labs.hk/migen/tutorial.pdf
Below is what I've got but I get error:
<Signal led at 0x102589128>
0
File "/Users/nyholku/migen-workspace/migen-experiments/src/leblinker.py", line 34,
in <module>
my_blinker.do_simulation(my_blinker)
File "/Users/nyholku/migen-workspace/migen-experiments/src/leblinker.py",
line 22, in do_simulation
if v_led != self.v_led_old:
File "/Users/nyholku/migen/migen/fhdl/structure.py", line 40, in __bool__
raise TypeError("Attempted to convert Migen value to boolean")
TypeError: Attempted to convert Migen value to boolean
An since I'm not too familiar with Python I don't understand why
this 'if v_led != self.v_led_old' is acceptable to the interpreter?
wbr Kusti
from random import Random
from migen import *
from migen.fhdl import verilog
class Blinker(Module):
def __init__(self, led, maxperiod):
self.led = led
self.v_led_old = 0
counter = Signal(max=maxperiod+1)
period = Signal(max=maxperiod+1)
self.comb += period.eq(maxperiod)
self.sync += If(counter == 0,
led.eq(~led),
counter.eq(period)
).Else(
counter.eq(counter - 1)
)
def do_simulation(self, selfp):
v_led = selfp.led # read the current signal value
print (v_led)
print (self.v_led_old)
if v_led != self.v_led_old:
print("{old}->{new} cycle={cycle}".format(
old=self.v_led_old,
new=v_led,
cycle=selfp.cycle_counter)
)
self.v_led_old = v_led
if __name__ == "__main__":
led = Signal()
my_blinker = Blinker(led, 30000000)
# run_simulation(my_blinker, tb(my_blinker), vcd_name="ledblinker.vcd")
my_blinker.do_simulation(my_blinker)
print(verilog.convert(my_blinker, ios={led}))
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