On 15/12/2017 12:13, "Devel on behalf of Sébastien Bourdeauducq"
<devel-boun...@lists.m-labs.hk on behalf of s...@m-labs.hk> wrote:
>Yeah just one &. Anyway the Python bitwise operators must be used
>everywhere (be careful of precedence).
Ok, thanks, that works and seems to compile fine to Verilog.
In general does this work ok in the sense that when I want bitwise ops I get
bitwise and when I need locical op I get that?
Would it make sense to implement and/or to separate logical and bitwise ops in
Migen?
wbr Kusti
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