Hi
I am experimenting with simulation of a hierarchical (using instances and
specials) FHDL design and I am having difficulty getting the simulator to
work. I always get the following error:
raise ValueError("Could not lower all specials", self.fragment.specials)
ValueError: ('Could not lower all specials', {<migen.fhdl.specials.Instance
object at 0x7eff08dfb0b8>, <migen.fhdl.specials.Instance object at
0x7eff08df77f0>})
I am aware that migen does not have support for simulating external Verilog
instances.
Does it also lack support for simulating hierarchical FHDL instances?
--
Khobatha Setetemela
*Department of Mathematics and Computer Science*
*National University of Lesothophone(cell): 59105441phone(office):
+2665221-3491*
*skype: oksetetemela*
website: http://www.nul.ls/
*"But seek ye first the kingdom of God, and His righteousness; and all
these things shall be added unto you" (Matt 6:33)*
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