Hello, I am Staf Verhaegen and I developing an open source ASIC project. I am now investigating use of Migen/MiSoC to implement the peripherals for microcontroller. First I just want to make a verilog block to be included in my existing design and then later maybe convert the whole Retro-uC to Migen/MiSoC. I did want to include I2C and SPI peripherals but when I do it with the latest version of MiSoC it generates RTL using the high impedant z value which not ASIC compatible. I adapted the cores to allow having a tristate input as a Record in this commit. With this commit applied I can then generate my (unfinished) subblock with the attached python script. Also the output is attached showing no z. This is basically untest for the moment, just looked at the generated verilog.
I am interested to know if the change to MiSoC is the direction to go for such a change. If OK, I can do a PR on github. If not, I would like to discuss alternative solutions. greets, Staf.
#!/bin/env python3
from migen import *
from migen.fhdl.verilog import convert
from misoc.cores.uart import RS232PHY, UART
from misoc.cores.spi2 import SPIInterface, SPIMaster
from misoc.cores.i2c import I2CMaster
class Peripherals(Module):
def __init__(self, clk_frequency):
ios = set()
# UART
r = Record([("rx", 1), ("tx", 1)], "uart")
phy = RS232PHY(r, clk_frequency)
self.submodules.uart_phy = phy
self.submodules.uart = UART(phy)
ios |= {r.rx, r.tx}
# SPI
r = Record([
("cs_n", [("i", 1), ("o", 1), ("oe", 1)]),
("clk", [("i", 1), ("o", 1), ("oe", 1)]),
("miso", [("i", 1), ("o", 1), ("oe", 1)]),
("mosi", [("i", 1), ("o", 1), ("oe", 1)])
], name="spi")
interface = SPIInterface(r)
self.submodules.spi_interface = interface
self.submodules.spi = SPIMaster(interface)
ios |= {
r.cs_n.i, r.cs_n.o, r.cs_n.oe,
r.clk.i, r.clk.o, r.clk.oe,
r.miso.i, r.miso.o, r.miso.oe,
r.mosi.i, r.mosi.o, r.mosi.oe
}
# I2C
r = Record([
("scl", [("i", 1), ("o", 1), ("oe", 1)]),
("sda", [("i", 1), ("o", 1), ("oe", 1)])
], name="i2c")
self.submodules.i2c = i2c = I2CMaster(r)
ios |= {
r.scl.i, r.scl.o, r.scl.oe,
r.sda.i, r.sda.o, r.sda.oe
}
# end
self.ios = ios
def verilog(self, filename="Peripherals.v", asic_syntax=True):
convert(self, self.ios, name="Peripherals", asic_syntax=asic_syntax).write(filename)
freq = 10*1000*1000
Peripherals(freq).verilog()
/* Machine-generated using Migen */
module Peripherals(
input uart_rx,
output reg uart_tx,
input spi_cs_n_i,
output reg spi_cs_n_o,
output spi_cs_n_oe,
input spi_clk_i,
output reg spi_clk_o,
output spi_clk_oe,
input spi_miso_i,
output spi_miso_o,
output spi_miso_oe,
input spi_mosi_i,
output spi_mosi_o,
output spi_mosi_oe,
input i2c_scl_i,
output i2c_scl_o,
output i2c_scl_oe,
input i2c_sda_i,
output i2c_sda_o,
output i2c_sda_oe,
input sys_clk,
input sys_rst
);
reg [31:0] phy_storage;
wire phy_sink_stb;
reg phy_sink_ack;
wire phy_sink_eop;
wire [7:0] phy_sink_payload_data;
reg phy_uart_clk_txen;
reg [31:0] phy_phase_accumulator_tx;
reg [7:0] phy_tx_reg;
reg [3:0] phy_tx_bitcount;
reg phy_tx_busy;
reg phy_source_stb;
wire phy_source_ack;
reg phy_source_eop;
reg [7:0] phy_source_payload_data;
reg phy_uart_clk_rxen;
reg [31:0] phy_phase_accumulator_rx;
wire phy_rx;
reg phy_rx_r;
reg [7:0] phy_rx_reg;
reg [3:0] phy_rx_bitcount;
reg phy_rx_busy;
reg uart_rxtx_re;
reg [7:0] uart_rxtx_r;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_rxempty_status;
wire uart_irq;
wire uart_tx_status;
reg uart_tx_pending;
wire uart_tx_trigger;
reg uart_tx_clear;
reg uart_tx_old_trigger;
wire uart_rx_status;
reg uart_rx_pending;
wire uart_rx_trigger;
reg uart_rx_clear;
reg uart_rx_old_trigger;
reg [1:0] uart_status_w;
reg uart_pending_re;
reg [1:0] uart_pending_r;
reg [1:0] uart_pending_w;
reg [1:0] uart_storage;
wire uart_tx_fifo_sink_stb;
wire uart_tx_fifo_sink_ack;
reg uart_tx_fifo_sink_eop;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_stb;
wire uart_tx_fifo_source_ack;
wire uart_tx_fifo_source_eop;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [8:0] uart_tx_fifo_syncfifo_din;
wire [8:0] uart_tx_fifo_syncfifo_dout;
reg [4:0] uart_tx_fifo_level;
reg uart_tx_fifo_replace;
reg [3:0] uart_tx_fifo_produce;
reg [3:0] uart_tx_fifo_consume;
reg [3:0] uart_tx_fifo_wrport_adr;
wire [8:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [8:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [8:0] uart_tx_fifo_rdport_dat_r;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_eop;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_eop;
wire uart_rx_fifo_sink_stb;
wire uart_rx_fifo_sink_ack;
wire uart_rx_fifo_sink_eop;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_stb;
wire uart_rx_fifo_source_ack;
wire uart_rx_fifo_source_eop;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [8:0] uart_rx_fifo_syncfifo_din;
wire [8:0] uart_rx_fifo_syncfifo_dout;
reg [4:0] uart_rx_fifo_level;
reg uart_rx_fifo_replace;
reg [3:0] uart_rx_fifo_produce;
reg [3:0] uart_rx_fifo_consume;
reg [3:0] uart_rx_fifo_wrport_adr;
wire [8:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [8:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [8:0] uart_rx_fifo_rdport_dat_r;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_eop;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_eop;
wire [2:0] interface_cs;
wire [2:0] interface_cs_polarity;
wire interface_clk_next;
wire interface_clk_polarity;
wire interface_cs_next;
wire interface_ce;
wire interface_sample;
wire interface_offline;
wire interface_half_duplex;
reg interface_sdi;
wire interface_sdo;
reg interface_miso_reg;
reg interface_mosi_reg;
reg [31:0] spi_data_storage;
reg spi_data_re;
wire spi_data_we;
wire [31:0] spi_data_dat_w;
reg [4:0] spi_length_storage;
reg [2:0] spi_cs_storage;
reg [2:0] spi_cs_polarity_storage;
reg [7:0] spi_div_storage;
reg spi_offline_storage;
reg spi_clk_polarity_storage;
reg spi_clk_phase_storage;
reg spi_lsb_first_storage;
reg spi_half_duplex_storage;
reg spi_end_storage;
wire spi_readable_status;
wire spi_writable_status;
wire spi_idle_status;
wire [4:0] spi_length;
wire spi_clk_phase;
reg spi_clk_next;
reg spi_cs_next;
wire spi_ce;
reg spi_idle;
wire spi_load0;
reg spi_readable;
reg spi_writable;
wire spi_end0;
wire [31:0] spi_pdo;
wire [31:0] spi_pdi;
reg spi_sdo;
wire spi_sdi;
wire spi_lsb_first;
reg spi_load1;
reg spi_shift;
reg spi_sample;
reg [31:0] spi_sr;
wire [7:0] spi_div;
reg spi_extend;
wire spi_done;
reg spi_count;
reg [6:0] spi_cnt;
wire spi_cnt_done;
reg spi_do_extend;
reg [4:0] spi_n;
reg spi_end1;
reg [29:0] i2c_bus_adr;
reg [31:0] i2c_bus_dat_w;
reg [31:0] i2c_bus_dat_r;
reg i2c_bus_cyc;
reg i2c_bus_stb;
reg i2c_bus_ack;
reg i2c_bus_we;
reg i2c_scl_o1;
reg i2c_sda_o1;
wire i2c_sda_i1;
reg [19:0] i2c_load;
wire i2c_clk2x;
reg [19:0] i2c_cnt;
wire i2c_cg_ce;
wire i2c_idle;
reg i2c_start;
reg i2c_stop;
reg i2c_write;
reg i2c_read;
reg i2c_ack;
reg [7:0] i2c_data;
reg [3:0] i2c_bits;
wire i2c_fsm_ce;
wire i2c_run;
reg i2c_fsm_is_ongoing;
reg [2:0] spimaster_state;
reg [2:0] spimaster_next_state;
reg [3:0] i2cmaster_state;
reg [3:0] i2cmaster_next_state;
reg [3:0] i2c_bits_next_value0;
reg i2c_bits_next_value_ce0;
reg i2c_scl_o1_next_value1;
reg i2c_scl_o1_next_value_ce1;
reg i2c_sda_o1_next_value2;
reg i2c_sda_o1_next_value_ce2;
reg [6:0] i2cmaster_next_value0;
reg i2cmaster_next_value_ce0;
reg i2c_ack_next_value3;
reg i2c_ack_next_value_ce3;
reg i2cmaster_next_value1;
reg i2cmaster_next_value_ce1;
(* no_retiming = "true" *) reg regs0;
(* no_retiming = "true" *) reg regs1;
assign uart_tx_fifo_sink_stb = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_txfull_status = (~uart_tx_fifo_sink_ack);
assign phy_sink_stb = uart_tx_fifo_source_stb;
assign uart_tx_fifo_source_ack = phy_sink_ack;
assign phy_sink_eop = uart_tx_fifo_source_eop;
assign phy_sink_payload_data = uart_tx_fifo_source_payload_data;
assign uart_tx_trigger = (~uart_tx_fifo_sink_ack);
assign uart_rx_fifo_sink_stb = phy_source_stb;
assign phy_source_ack = uart_rx_fifo_sink_ack;
assign uart_rx_fifo_sink_eop = phy_source_eop;
assign uart_rx_fifo_sink_payload_data = phy_source_payload_data;
assign uart_rxempty_status = (~uart_rx_fifo_source_stb);
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ack = uart_rx_clear;
assign uart_rx_trigger = (~uart_rx_fifo_source_stb);
always @(*) begin
uart_tx_clear = 1'd0;
if ((uart_pending_re & uart_pending_r[0])) begin
uart_tx_clear = 1'd1;
end
end
always @(*) begin
uart_status_w = 2'd0;
uart_status_w[0] = uart_tx_status;
uart_status_w[1] = uart_rx_status;
end
always @(*) begin
uart_rx_clear = 1'd0;
if ((uart_pending_re & uart_pending_r[1])) begin
uart_rx_clear = 1'd1;
end
end
always @(*) begin
uart_pending_w = 2'd0;
uart_pending_w[0] = uart_tx_pending;
uart_pending_w[1] = uart_rx_pending;
end
assign uart_irq = ((uart_pending_w[0] & uart_storage[0]) | (uart_pending_w[1] & uart_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_eop, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_eop, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ack = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_stb;
assign uart_tx_fifo_fifo_in_eop = uart_tx_fifo_sink_eop;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_stb = uart_tx_fifo_syncfifo_readable;
assign uart_tx_fifo_source_eop = uart_tx_fifo_fifo_out_eop;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_syncfifo_re = uart_tx_fifo_source_ack;
always @(*) begin
uart_tx_fifo_wrport_adr = 4'd0;
if (uart_tx_fifo_replace) begin
uart_tx_fifo_wrport_adr = (uart_tx_fifo_produce - 1'd1);
end else begin
uart_tx_fifo_wrport_adr = uart_tx_fifo_produce;
end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_eop, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_eop, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ack = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_stb;
assign uart_rx_fifo_fifo_in_eop = uart_rx_fifo_sink_eop;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_stb = uart_rx_fifo_syncfifo_readable;
assign uart_rx_fifo_source_eop = uart_rx_fifo_fifo_out_eop;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_syncfifo_re = uart_rx_fifo_source_ack;
always @(*) begin
uart_rx_fifo_wrport_adr = 4'd0;
if (uart_rx_fifo_replace) begin
uart_rx_fifo_wrport_adr = (uart_rx_fifo_produce - 1'd1);
end else begin
uart_rx_fifo_wrport_adr = uart_rx_fifo_produce;
end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level != 1'd0);
assign spi_miso_oe = 1'd0;
assign spi_mosi_o = interface_sdo;
assign spi_miso_o = interface_sdo;
assign spi_cs_n_oe = (~interface_offline);
assign spi_clk_oe = (~interface_offline);
assign spi_mosi_oe = (~(interface_offline | interface_half_duplex));
always @(*) begin
interface_sdi = 1'd0;
if ((interface_cs[0] != 1'd0)) begin
interface_sdi = (interface_half_duplex ? interface_mosi_reg : interface_miso_reg);
end
end
assign spi_pdo = spi_data_storage;
assign spi_data_dat_w = spi_pdi;
assign spi_data_we = spi_readable;
assign spi_length = spi_length_storage;
assign spi_end0 = spi_end_storage;
assign spi_div = spi_div_storage;
assign spi_load0 = spi_data_re;
assign spi_clk_phase = spi_clk_phase_storage;
assign spi_lsb_first = spi_lsb_first_storage;
assign spi_readable_status = spi_readable;
assign spi_writable_status = spi_writable;
assign spi_idle_status = spi_idle;
assign interface_half_duplex = spi_half_duplex_storage;
assign interface_cs = spi_cs_storage;
assign interface_cs_polarity = spi_cs_polarity_storage;
assign interface_clk_polarity = spi_clk_polarity_storage;
assign interface_offline = spi_offline_storage;
assign interface_cs_next = spi_cs_next;
assign interface_clk_next = spi_clk_next;
assign interface_ce = spi_ce;
assign interface_sample = spi_sample;
assign spi_sdi = interface_sdi;
assign interface_sdo = spi_sdo;
assign spi_ce = (spi_done & spi_count);
assign spi_pdi = (spi_lsb_first ? {spi_sdi, spi_sr[31:1]} : {spi_sr[30:0], spi_sdi});
assign spi_cnt_done = (spi_cnt == 1'd0);
assign spi_done = (spi_cnt_done & (~spi_do_extend));
always @(*) begin
spi_clk_next = 1'd0;
spi_cs_next = 1'd0;
spi_idle = 1'd0;
spi_readable = 1'd0;
spi_writable = 1'd0;
spi_load1 = 1'd0;
spi_shift = 1'd0;
spi_sample = 1'd0;
spi_extend = 1'd0;
spi_count = 1'd0;
spimaster_next_state = 3'd0;
spimaster_next_state = spimaster_state;
case (spimaster_state)
1'd1: begin
spi_cs_next = 1'd1;
spi_count = 1'd1;
spi_extend = 1'd1;
spi_clk_next = 1'd1;
if (spi_done) begin
spimaster_next_state = 2'd2;
end
end
2'd2: begin
spi_cs_next = 1'd1;
spi_count = 1'd1;
spi_clk_next = (~spi_clk_phase);
if (spi_done) begin
spi_sample = 1'd1;
spimaster_next_state = 2'd3;
end
end
2'd3: begin
spi_cs_next = 1'd1;
spi_count = 1'd1;
spi_extend = 1'd1;
spi_clk_next = spi_clk_phase;
if (spi_done) begin
if ((spi_n == 1'd0)) begin
spi_readable = 1'd1;
spi_writable = 1'd1;
if (spi_end1) begin
spi_clk_next = 1'd0;
spi_writable = 1'd0;
if (spi_clk_phase) begin
spi_cs_next = 1'd0;
spimaster_next_state = 3'd5;
end else begin
spimaster_next_state = 3'd4;
end
end else begin
if (spi_load0) begin
spi_load1 = 1'd1;
spimaster_next_state = 2'd2;
end else begin
spi_count = 1'd0;
end
end
end else begin
spi_shift = 1'd1;
spimaster_next_state = 2'd2;
end
end
end
3'd4: begin
spi_count = 1'd1;
if (spi_done) begin
spimaster_next_state = 3'd5;
end
end
3'd5: begin
if (spi_done) begin
spimaster_next_state = 1'd0;
end else begin
spi_count = 1'd1;
end
end
default: begin
spi_idle = 1'd1;
spi_writable = 1'd1;
spi_cs_next = 1'd1;
if (spi_load0) begin
spi_count = 1'd1;
spi_load1 = 1'd1;
if (spi_clk_phase) begin
spimaster_next_state = 1'd1;
end else begin
spi_extend = 1'd1;
spimaster_next_state = 2'd2;
end
end
end
endcase
end
assign i2c_scl_oe = (~i2c_scl_o1);
assign i2c_scl_o = 1'd0;
assign i2c_sda_oe = (~i2c_sda_o1);
assign i2c_sda_o = 1'd0;
assign i2c_sda_i1 = i2c_sda_i;
assign i2c_run = (((i2c_start | i2c_stop) | i2c_write) | i2c_read);
assign i2c_idle = ((~i2c_run) & i2c_fsm_is_ongoing);
assign i2c_cg_ce = (~i2c_idle);
assign i2c_fsm_ce = (i2c_run | i2c_clk2x);
assign i2c_clk2x = (i2c_cnt == 1'd0);
always @(*) begin
i2c_fsm_is_ongoing = 1'd0;
i2cmaster_next_state = 4'd0;
i2c_bits_next_value0 = 4'd0;
i2c_bits_next_value_ce0 = 1'd0;
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd0;
i2c_sda_o1_next_value2 = 1'd0;
i2c_sda_o1_next_value_ce2 = 1'd0;
i2cmaster_next_value0 = 7'd0;
i2cmaster_next_value_ce0 = 1'd0;
i2c_ack_next_value3 = 1'd0;
i2c_ack_next_value_ce3 = 1'd0;
i2cmaster_next_value1 = 1'd0;
i2cmaster_next_value_ce1 = 1'd0;
i2cmaster_next_state = i2cmaster_state;
case (i2cmaster_state)
1'd1: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_state = 2'd2;
end
2'd2: begin
i2c_sda_o1_next_value2 = 1'd0;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 1'd0;
end
2'd3: begin
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_state = 3'd4;
end
3'd4: begin
i2c_sda_o1_next_value2 = 1'd1;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 1'd1;
end
3'd5: begin
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_state = 3'd6;
end
3'd6: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2c_sda_o1_next_value2 = 1'd0;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 3'd7;
end
3'd7: begin
i2c_sda_o1_next_value2 = 1'd1;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 1'd0;
end
4'd8: begin
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd1;
if ((i2c_bits == 1'd0)) begin
i2c_sda_o1_next_value2 = 1'd1;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 4'd10;
end else begin
i2c_sda_o1_next_value2 = i2c_data[7];
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 4'd9;
end
end
4'd9: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_value0 = i2c_data[6:0];
i2cmaster_next_value_ce0 = 1'd1;
i2c_bits_next_value0 = (i2c_bits - 1'd1);
i2c_bits_next_value_ce0 = 1'd1;
i2cmaster_next_state = 4'd8;
end
4'd10: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_state = 4'd11;
end
4'd11: begin
i2c_ack_next_value3 = (~i2c_sda_i1);
i2c_ack_next_value_ce3 = 1'd1;
i2cmaster_next_state = 1'd0;
end
4'd12: begin
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2c_sda_o1_next_value2 = 1'd1;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 4'd13;
end
4'd13: begin
i2cmaster_next_value1 = i2c_sda_i1;
i2cmaster_next_value_ce1 = 1'd1;
i2c_scl_o1_next_value1 = 1'd0;
i2c_scl_o1_next_value_ce1 = 1'd1;
if ((i2c_bits == 1'd0)) begin
i2c_sda_o1_next_value2 = (~i2c_ack);
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 4'd15;
end else begin
i2c_sda_o1_next_value2 = 1'd1;
i2c_sda_o1_next_value_ce2 = 1'd1;
i2cmaster_next_state = 4'd14;
end
end
4'd14: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_value0 = i2c_data[6:0];
i2cmaster_next_value_ce0 = 1'd1;
i2c_bits_next_value0 = (i2c_bits - 1'd1);
i2c_bits_next_value_ce0 = 1'd1;
i2cmaster_next_state = 4'd13;
end
4'd15: begin
i2c_scl_o1_next_value1 = 1'd1;
i2c_scl_o1_next_value_ce1 = 1'd1;
i2cmaster_next_state = 1'd0;
end
default: begin
if (i2c_start) begin
i2cmaster_next_state = 1'd1;
end else begin
if ((i2c_stop & i2c_start)) begin
i2cmaster_next_state = 2'd3;
end else begin
if (i2c_stop) begin
i2cmaster_next_state = 3'd5;
end else begin
if (i2c_write) begin
i2c_bits_next_value0 = 4'd8;
i2c_bits_next_value_ce0 = 1'd1;
i2cmaster_next_state = 4'd8;
end else begin
if (i2c_read) begin
i2c_bits_next_value0 = 4'd8;
i2c_bits_next_value_ce0 = 1'd1;
i2cmaster_next_state = 4'd12;
end
end
end
end
end
i2c_fsm_is_ongoing = 1'd1;
end
endcase
end
assign phy_rx = regs1;
always @(posedge sys_clk) begin
phy_sink_ack <= 1'd0;
if (((phy_sink_stb & (~phy_tx_busy)) & (~phy_sink_ack))) begin
phy_tx_reg <= phy_sink_payload_data;
phy_tx_bitcount <= 1'd0;
phy_tx_busy <= 1'd1;
uart_tx <= 1'd0;
end else begin
if ((phy_uart_clk_txen & phy_tx_busy)) begin
phy_tx_bitcount <= (phy_tx_bitcount + 1'd1);
if ((phy_tx_bitcount == 4'd8)) begin
uart_tx <= 1'd1;
end else begin
if ((phy_tx_bitcount == 4'd9)) begin
uart_tx <= 1'd1;
phy_tx_busy <= 1'd0;
phy_sink_ack <= 1'd1;
end else begin
uart_tx <= phy_tx_reg[0];
phy_tx_reg <= {1'd0, phy_tx_reg[7:1]};
end
end
end
end
if (phy_tx_busy) begin
{phy_uart_clk_txen, phy_phase_accumulator_tx} <= (phy_phase_accumulator_tx + phy_storage);
end else begin
{phy_uart_clk_txen, phy_phase_accumulator_tx} <= 1'd0;
end
phy_source_stb <= 1'd0;
phy_rx_r <= phy_rx;
if ((~phy_rx_busy)) begin
if (((~phy_rx) & phy_rx_r)) begin
phy_rx_busy <= 1'd1;
phy_rx_bitcount <= 1'd0;
end
end else begin
if (phy_uart_clk_rxen) begin
phy_rx_bitcount <= (phy_rx_bitcount + 1'd1);
if ((phy_rx_bitcount == 1'd0)) begin
if (phy_rx) begin
phy_rx_busy <= 1'd0;
end
end else begin
if ((phy_rx_bitcount == 4'd9)) begin
phy_rx_busy <= 1'd0;
if (phy_rx) begin
phy_source_payload_data <= phy_rx_reg;
phy_source_stb <= 1'd1;
end
end else begin
phy_rx_reg <= {phy_rx, phy_rx_reg[7:1]};
end
end
end
end
if (phy_rx_busy) begin
{phy_uart_clk_rxen, phy_phase_accumulator_rx} <= (phy_phase_accumulator_rx + phy_storage);
end else begin
{phy_uart_clk_rxen, phy_phase_accumulator_rx} <= 32'd2147483648;
end
if (uart_tx_clear) begin
uart_tx_pending <= 1'd0;
end
uart_tx_old_trigger <= uart_tx_trigger;
if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
uart_tx_pending <= 1'd1;
end
if (uart_rx_clear) begin
uart_rx_pending <= 1'd0;
end
uart_rx_old_trigger <= uart_rx_trigger;
if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
uart_rx_pending <= 1'd1;
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
end
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
if ((~uart_tx_fifo_do_read)) begin
uart_tx_fifo_level <= (uart_tx_fifo_level + 1'd1);
end
end else begin
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_level <= (uart_tx_fifo_level - 1'd1);
end
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
end
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
if ((~uart_rx_fifo_do_read)) begin
uart_rx_fifo_level <= (uart_rx_fifo_level + 1'd1);
end
end else begin
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_level <= (uart_rx_fifo_level - 1'd1);
end
end
if (interface_ce) begin
spi_cs_n_o <= (({1{interface_cs_next}} & interface_cs[0]) ^ (~interface_cs_polarity[0]));
spi_clk_o <= (interface_clk_next ^ interface_clk_polarity);
end
if (interface_sample) begin
interface_miso_reg <= spi_miso_i;
interface_mosi_reg <= spi_mosi_i;
end
if (spi_load1) begin
spi_n <= spi_length;
spi_end1 <= spi_end0;
end
if (spi_shift) begin
spi_n <= (spi_n - 1'd1);
end
if (spi_shift) begin
spi_sr <= spi_pdi;
spi_sdo <= (spi_lsb_first ? spi_pdi[0] : spi_pdi[31]);
end
if (spi_load1) begin
spi_sr <= spi_pdo;
spi_sdo <= (spi_lsb_first ? spi_pdo[0] : spi_pdo[31]);
end
if (spi_count) begin
if (spi_cnt_done) begin
if (spi_do_extend) begin
spi_do_extend <= 1'd0;
end else begin
spi_cnt <= spi_div[7:1];
spi_do_extend <= (spi_extend & spi_div[0]);
end
end else begin
spi_cnt <= (spi_cnt - 1'd1);
end
end
spimaster_state <= spimaster_next_state;
if (i2c_bus_adr[0]) begin
i2c_bus_dat_r <= i2c_load;
end else begin
i2c_bus_dat_r <= {i2c_idle, 4'd0, i2c_ack, i2c_data};
end
i2c_read <= 1'd0;
i2c_write <= 1'd0;
i2c_start <= 1'd0;
i2c_stop <= 1'd0;
i2c_bus_ack <= 1'd0;
if (((i2c_bus_cyc & i2c_bus_stb) & (~i2c_bus_ack))) begin
i2c_bus_ack <= 1'd1;
if (i2c_bus_we) begin
if (i2c_bus_adr[0]) begin
i2c_load <= i2c_bus_dat_w;
end else begin
i2c_data <= i2c_bus_dat_w[7:0];
i2c_ack <= i2c_bus_dat_w[8];
i2c_read <= i2c_bus_dat_w[9];
i2c_write <= i2c_bus_dat_w[10];
i2c_start <= i2c_bus_dat_w[11];
i2c_stop <= i2c_bus_dat_w[12];
end
end
end
if (i2c_cg_ce) begin
if (i2c_clk2x) begin
i2c_cnt <= i2c_load;
end else begin
i2c_cnt <= (i2c_cnt - 1'd1);
end
end
if (i2c_fsm_ce) begin
i2cmaster_state <= i2cmaster_next_state;
if (i2c_bits_next_value_ce0) begin
i2c_bits <= i2c_bits_next_value0;
end
if (i2c_scl_o1_next_value_ce1) begin
i2c_scl_o1 <= i2c_scl_o1_next_value1;
end
if (i2c_sda_o1_next_value_ce2) begin
i2c_sda_o1 <= i2c_sda_o1_next_value2;
end
if (i2cmaster_next_value_ce0) begin
i2c_data[7:1] <= i2cmaster_next_value0;
end
if (i2c_ack_next_value_ce3) begin
i2c_ack <= i2c_ack_next_value3;
end
if (i2cmaster_next_value_ce1) begin
i2c_data[0] <= i2cmaster_next_value1;
end
end
if (sys_rst) begin
uart_tx <= 1'd1;
phy_sink_ack <= 1'd0;
phy_uart_clk_txen <= 1'd0;
phy_phase_accumulator_tx <= 32'd0;
phy_tx_reg <= 8'd0;
phy_tx_bitcount <= 4'd0;
phy_tx_busy <= 1'd0;
phy_source_stb <= 1'd0;
phy_source_payload_data <= 8'd0;
phy_uart_clk_rxen <= 1'd0;
phy_phase_accumulator_rx <= 32'd0;
phy_rx_r <= 1'd0;
phy_rx_reg <= 8'd0;
phy_rx_bitcount <= 4'd0;
phy_rx_busy <= 1'd0;
uart_tx_pending <= 1'd0;
uart_tx_old_trigger <= 1'd0;
uart_rx_pending <= 1'd0;
uart_rx_old_trigger <= 1'd0;
uart_tx_fifo_level <= 5'd0;
uart_tx_fifo_produce <= 4'd0;
uart_tx_fifo_consume <= 4'd0;
uart_rx_fifo_level <= 5'd0;
uart_rx_fifo_produce <= 4'd0;
uart_rx_fifo_consume <= 4'd0;
spi_cs_n_o <= 1'd0;
spi_clk_o <= 1'd0;
spi_cnt <= 7'd0;
spi_do_extend <= 1'd0;
i2c_bus_dat_r <= 32'd0;
i2c_bus_ack <= 1'd0;
i2c_scl_o1 <= 1'd1;
i2c_sda_o1 <= 1'd1;
i2c_load <= 20'd0;
i2c_cnt <= 20'd0;
i2c_start <= 1'd0;
i2c_stop <= 1'd0;
i2c_write <= 1'd0;
i2c_read <= 1'd0;
i2c_ack <= 1'd0;
i2c_data <= 8'd0;
i2c_bits <= 4'd0;
spimaster_state <= 3'd0;
i2cmaster_state <= 4'd0;
end
regs0 <= uart_rx;
regs1 <= regs0;
end
reg [8:0] storage[0:15];
reg [8:0] memdat;
always @(posedge sys_clk) begin
if (uart_tx_fifo_wrport_we)
storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
memdat <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign uart_tx_fifo_wrport_dat_r = memdat;
assign uart_tx_fifo_rdport_dat_r = storage[uart_tx_fifo_rdport_adr];
reg [8:0] storage_1[0:15];
reg [8:0] memdat_1;
always @(posedge sys_clk) begin
if (uart_rx_fifo_wrport_we)
storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
memdat_1 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign uart_rx_fifo_wrport_dat_r = memdat_1;
assign uart_rx_fifo_rdport_dat_r = storage_1[uart_rx_fifo_rdport_adr];
endmodule
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