Hi Takeshi, I have seen from your last commit that you plan to ack the PS/2 interrupts by reading to a register you have added.
Since the CSR bus has no read enable signal, it is good design practice that read cycles do not modify the state of your core. Otherwise, when the address lines go invalid (which in the Milkymist SoC happens whenever the Wishbone address lines are invalid - Wishbone does have a read enable mechanism) they can cause an accidental read of your interrupt register and therefore an unwanted sporadic acknowledgment of the PS/2 interrupt, leading to hard-to-find bugs. So, you should change your design so that the interrupt is acknowledged when the register is *written* (csr_we=1) as it is done in other cores that use interrupts. Best regards, Sébastien _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
