On Wednesday 20 January 2010 15:54:34 Zeus Gómez Marmolejo wrote:
> Another thing I would like to add. The performance of the FML bridge could
> be slightly improved. Think about this situation: while it is doing a
>  REFILL (due to a previous wishbone read or write transaction) and a read
>  operation comes meanwhile, it has to wait till all the refill operation
>  has completed in order to check the cache hit and return data. But if the
>  read is already a hit, there's no need to wait and the data can be
>  returned immediately.

Yes and there is a load of similar tricks all over the system that could 
improve performance further. Lack of time prevents me from coding most of 
them; and "if it's not broken, don't fix it".

For this one, another problem is that a dual-port RAM is required, and I am 
already planning to use the second port to implement cache coherency for the 
VGA output framebuffer - maintaining coherency with software is too much of a 
mess.

Thank you for the test bench. I will review it, perform more tests on HPDMC 
and most probably merge it along with your patch.

Sébastien
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