Hi Paul,
I'm not sure if you are still maintaining VCOMP [1], but I'm trying to use it
to debug the texture mapping unit in Milkymist [2], an open source hardware
SoC with 2D acceleration. Being a "compiled" simulator, I hope it would bring
speed advantages over GPL Cver that I'm currently using (full simulations of
the texture mapping unit typically take several minutes on a fast machine).
I have noticed two problems:
* most importantly, blocking assignments sometimes do not work as expected,
for example in the following code excerpt:
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive) begin
o = o + {1'b0, q_r}; // A
if(correct)
o = o + 18'd1; // B
end else begin
o = o - {1'b0, q_r}; // A'
if(correct)
o = o - 18'd1; // B'
end
If correct evaluates to true, then only lines B or B' are taken into account
(not A and A'), yielding a wrong value for o (only incremented/decremented by
1 while it should _also_ be added/subtracted {1'b0, q_r}). I am attaching the
full source code that provokes the problem.
* VCOMP does not support the Verilog-2001 syntax "output reg signed" in module
port declarations.
Thanks for any feedback,
Sébastien
[1] http://vcomp.sf.net
[2] http://www.milkymist.org
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output reg signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
always @(posedge sys_clk) begin
if(load) begin
err <= 18'd0;
o <= init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive) begin
o = o + {1'b0, q_r};
if(correct)
o = o + 18'd1;
end else begin
o = o - {1'b0, q_r};
if(correct)
o = o - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule
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