Helo I am completely new to FPGA's, but have used CPLD's as glue logic to microcontrollers for many years.
I have bought cheap board with Altera Cyclone III FPGA and MT48LC4M16A2 SDR SDRAM. Iwould like to use yadmc controller from milkymist project to acces the SDRAM. I have found and edited possibly all diferences between the original memory from your project. Yes, it is pretty good parametrized. But i encoutered this problem: The compilation in Quartus II has stopped after this message - Error: Cannot synthesize dual-port RAM logic "yadmc:SDR_controller| yadmc_dpram:cacheline2|storage" Is this of some incorrect setup, or is it realy not possible to implement dual-port ram in Cyclone III? Any clue? Thank you Jakub Ladman _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
