Hi, Ethernet is working, albeit with some FIFO under/overflow problems that stem from bugs in the FPGA design (not the PCB) that were already present in the ML401 design and appear more frequently here because of the lower system frequency used at the moment (83MHz instead of 100MHz). I will fix them later. Nonetheless, I have just been able to netboot a small Linux system on the M1.
I have also spotted a minor PCB error. At power-up, the KSZ8001 expects its (negative logic) reset pin to be low, but it is currently driven high by the pre-configuration weak pull-up resistors of the FPGA. This means that immediately after power is applied, there is a brief time during which the KSZ8001 is in an undefined state until the FPGA gets configured and resets the KSZ8001 properly. This does not prevent at all the prototype from working, however, I would prefer to stick closely to the chip specifications to avoid bad surprises during production. A simple fix can be to add a 10K pull-down resistor on ETH_RESET_N that will hold the KSZ8001 in reset until the configured FPGA drives the signal high. Sébastien _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
