Hi, UG380 p.50-51 states: "For many systems with near-simultaneous power supply ramps, the FPGA power-on reset time (tPOR) can sufficiently delay the start of the FPGA configuration procedure such that the parallel NOR flash becomes ready before the start of the FPGA configuration procedure."
This is the case of the RC1 prototypes (with the Intel flash chips). However, can we add a place-holder footprint for a DNP 0402 capacitor between PROGRAM_B (pin AA1, there's already a resistor connected there so it should be easy to add) and the ground so we can easily delay FPGA configuration by mounting the capacitor if we have any problem with some flash parts (possibly second sourced) being slow to power up and/or some FPGAs being fast to start (tPOR is characterized between 5ms and 40ms). The Numonyx flash chips that I originally picked had a power up time of 0.3ms... (Holding PROGRAM_B low to delay configuration is described on p. 51 and 73 of UG380). Most probably we won't need this extra capacitor, but it's a very simple thing to add and better safe than sorry :) Regards, S. _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Twitter: www.twitter.com/milkymistvj
