Forwarding to the mailing list so other people can comment. Thank you for your interest in the Navre core! S.
--- Begin Message ---Hi, I list some suggestion about navre mcu: 1. A bug, when unsupported instruction runs, GPR reg may be written. May can changed as this : 436,440c442,446 < 16'b0000_0000_0000_0000: begin < /* NOP */ < update_nsz = 1'b0; < writeback = 1'b0; < end --- > //16'b0000_0000_0000_0000: begin > // /* NOP */ > // update_nsz = 1'b0; > // writeback = 1'b0; > //end 467a474,477 > default: begin /* NOP and other*/ > writeback = 1'b0; > update_nsz = 1'b0; > end 2. For the lower 96(or 256) data memory locations the GPR register file and IO register file, so the access the lower address should map to GPR or IOF. 3. I have optimized Multi-cycle operation sequencer, please see the attachment. 4. In Asic design, Not recommended using X(such as R16 = 16'hxxxx), for mismatching in pre/post simulation. 5. Suggestion, The line242, suggest split 2 blocks, one is Nonblocking assignment and anther is blocking assignment. 6. Suggestion, add a navre enable signal for used as gate signal in asic synthesis(such as: compile -gated). Thanks
softusb_navre.v
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