On Sun, 2011-01-02 at 09:34 +0800, haimag ren wrote:
> As soft-core can be reused by others, strongly recommend you add
> these instructions or can use define to configure the code to be
> synthesized or not. When add interrupt, the interrupt IO file may
> used these instructions.
Yes if your goal is to make a generic AVR clone that everyone can use
with minimal homework, but mine was simply to get USB to work on
Milkymist. However, if you implement those features and send a proper
patch that does not break anything else, I'd happily merge it.
> Another question, for the lower 96(or 256) data memory are mapped to
> GPR register file and IO register file, so data memory(used by gcc)
> address start from 96/256, which file processing this mapping ?
> thanks.
The address bus is decoded in softusb_sie.v and softusb_timer.v, and the
outcomes from the reads (which are 0 when the modules are deselected)
are ORed together in softusb.v.
> BTW, the following code in softusb_navre.v,
>
> // !!! WARNING !!! replace with PC <= PC + {{pmem_width-12{Kl[11]}},
> Kl}; if pmem_width>12
> PC_SEL_KL: PC <= PC + Kl;
>
> can be changed to:
> PC_SEL_KL: PC <= PC + $signed(Kl);
>
> so others no need to changed this code.
True. Thanks for pointing this out. Shouldn't PC go through $signed() as
well? AFAIK, Verilog will only sign-extend an operand when both of them
are signed:
http://objectmix.com/verilog/189513-unsigned-signed-data-verilog.html
"Using $signed on one operand of an expression when there are still
other operands that are unsigned will not make anything
signed. The result will immediately be converted back
to unsigned, as with any signed operand in an
unsigned expression."
S.
PS: What is your project using Navre about?
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