On 10/03/11 12:28 AM, Michael Walle wrote:
First of all, i'm totally not against this ;) I was just curious.
Am Mittwoch 09 März 2011, 09:25:18 schrieb Wesley W. Terpstra:
The Cyclone3 chip has a 'sld hub' inside it which is accessed via two of
the Cyclone3's JTAG registers. You can instruct the hub via USER1 to
connect one of the JTAG instance ids' IR or DR to the USER0 register.
Is this a convention that you use one for IR and one for DR? Because atm the
lm32 jtag core uses just one register (and only one USER instruction).
Aha! I've now read
Xilinx Spartan-6 Libraries Guide for HDL Designs
<http://www.google.com/url?sa=t&source=web&cd=1&ved=0CCEQFjAA&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx11%2Fspartan6_hdl.pdf&ei=xYN4TaGIOcfIsgaoq63qBw&usg=AFQjCNFJ65JbXLb_BRG1R4i_Fp_GeR5MXw>
and I realize we're talking about different things.
According to my updated understanding of the Xilinx situation, you do
not create a subordinate JTAG chain there. Rather, the Spartan6 gives
you up to four registers for your use. The IR values those registers
correspond to are not under your control. The LM32 exposes its single
control register as one of these four pre-defined registers. This is
*not* the same as the Altera approach.
With Altera, there are USER0/1 registers on the 'upper level' JTAG just
like the Spartan6. Where things differ is that you do not connect your
design directly to these registers. Rather, the Altera sld hub is
connected to these registers. By controlling the sld hub, you may access
a number of subordinate JTAG chains connected to the sld hub. These
chains are "proper" JTAG chains: each its own IR and DR registers.
Other designs may already have a JTAG chain with
multiple devices that were originally connected directly to output pins
and you have now connected to the sld hub.
It seems this is impossible with the Xilinx approach. Since you don't
get to setup your own IR register, you can't port these easily. Rather
disappointing. It also means IDCODE and BYPASS are impossible to do for
Xilinx with the BSCAN_SPARTAN6 megafunction.
Perhaps there is an alternative JTAG approach/megafunction for the Xilinx?
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