Hello, I'm working on adding an adc-like core to the Milkymist SoC, it will acept data coming as spi-like or parallel bus.
The main porpuse is do some SDR processing and of course custom cores will be developed as needed to speedup some tasks. The plan is add this core to the system as master, so it can do DMA as the Minimac for example. One year ago i had read a doc about conbus. Now i'm not totally aware of some changes related with it, as the cross bar swich part plus a shared bus?. Is this part of a move for a "pluggable hdl cores"? So, for me, things a bit different hard to edit and adapt, due my inexperience so i'm requestinh help around: 1). Addressing: According to memmap.txt current addressing goes as follow: Peripheral WB base (L1 cached/uncached) ============================================================ NOR flash 0x00000000 / 0x80000000 SoftUSB shared memory 0x20000000 / 0xa0000000 FML bridge (SDRAM) 0x40000000 / 0xc0000000 CSR bridge 0x60000000 / 0xe0000000 Where/how i should put/address the new core?.I dont want break current software, but i guess some comments/guidelines about this is needed as other cores will arrive soon or later. 1). Coding: So, i guess i have to edit: xbar.v and conbus6x1 (also conbus_arb6.v) and follow the logic order like making gnt_dec register one bit bigger for the new master interface? (Actaully i already did this but dint tried yet to synthesize..) I have a last questions, i think can help me to clear some doubts and is about the SoftUSB core, why this core is maped as it is when is already a slave? Why not used the system memory as the minimac core? How is conbus2x5.v related with this and the FML? if related of course. I was hope i was at least a bit clear, in anycase i can ask again ;-) Cristian Paul
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