Hi, I see that the LM32 can have an 8kiB i-cache and an 8kiB d-cache.
I have not started looking at the specifics of the LM32 implementation for MilkyMist, but if cache was implemented then a careful choice of MMU and cache interaction will be needed, it seems. The reason I say this is that Marvell implemented a VIVT cache design on their 78x00 chips, and it turned out to be problematic. The performance of that chip was no where as good as it could have been with a better cache design, say, perhaps a VIPT cache, or perhaps even a PI indexed cache (but that means you cannot begin memory accesses in the cache until you have done virtual to physical translation, it seems to me). -- Regards, Richard Sharpe _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
