Diff file is atached, mm1 still booting, wich i guess is because i dint added a new core to the bus ;-)
I'll start with a second UART port. Then a DMA core. I ran from "/home/paul/milkymist/boards/milkymist-one/flash" the command: make | tee synthesis.log Build log http://kristianpaul.org/~paul/tmp/02-19-11_1synthesis.log
Added a 7th master
diff --git a/cores/conbus/rtl/conbus6x1.v b/cores/conbus/rtl/conbus6x1.v
index 378942b..fa0e7ce 100644
--- a/cores/conbus/rtl/conbus6x1.v
+++ b/cores/conbus/rtl/conbus6x1.v
@@ -96,6 +96,17 @@ module conbus6x1(
input m5_stb_i,
output m5_ack_o,
+ // Master 6 Interface
+ input [31:0] m6_dat_i,
+ output [31:0] m6_dat_o,
+ input [31:0] m6_adr_i,
+ input [2:0] m6_cti_i,
+ input [3:0] m6_sel_i,
+ input m6_we_i,
+ input m6_cyc_i,
+ input m6_stb_i,
+ output m6_ack_o,
+
// Slave Interface
input [31:0] s_dat_i,
output [31:0] s_dat_o,
@@ -118,16 +129,17 @@ wire [31:0] i_dat_s; // internal shared bus, slave data to master
wire i_bus_ack; // internal shared bus, ack signal
// !!!! This breaks WISHBONE combinatorial feedback. Don't use it !!!!
-reg [5:0] gnt_dec;
+reg [6:0] gnt_dec;
always @(posedge sys_clk) begin
case(gnt)
- 3'd0: gnt_dec <= 6'b000001;
- 3'd1: gnt_dec <= 6'b000010;
- 3'd2: gnt_dec <= 6'b000100;
- 3'd3: gnt_dec <= 6'b001000;
- 3'd4: gnt_dec <= 6'b010000;
- 3'd5: gnt_dec <= 6'b100000;
- default: gnt_dec <= 6'bxxxxxx;
+ 3'd0: gnt_dec <= 7'b0000001;
+ 3'd1: gnt_dec <= 7'b0000010;
+ 3'd2: gnt_dec <= 7'b0000100;
+ 3'd3: gnt_dec <= 7'b0001000;
+ 3'd4: gnt_dec <= 7'b0010000;
+ 3'd5: gnt_dec <= 7'b0100000;
+ 3'd6: gnt_dec <= 7'b1000000;
+ default: gnt_dec <= 7'bxxxxxxx;
endcase
end
// !!!! This breaks WISHBONE combinatorial feedback. Don't use it !!!!
@@ -156,6 +168,10 @@ assign m4_ack_o = i_bus_ack & gnt_dec[4];
assign m5_dat_o = i_dat_s;
assign m5_ack_o = i_bus_ack & gnt_dec[5];
+// master 6
+assign m6_dat_o = i_dat_s;
+assign m6_ack_o = i_bus_ack & gnt_dec[6];
+
assign i_bus_ack = s_ack_i;
// slave
@@ -169,13 +185,15 @@ always @(*) begin
3'd3: i_bus_m = {m3_adr_i, m3_cti_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cyc_i, m3_stb_i};
3'd4: i_bus_m = {m4_adr_i, m4_cti_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cyc_i, m4_stb_i};
3'd5: i_bus_m = {m5_adr_i, m5_cti_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cyc_i, m5_stb_i};
+ 3'd6: i_bus_m = {m6_adr_i, m6_cti_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cyc_i, m6_stb_i};
default: i_bus_m = {`mbusw_ls{1'bx}};
endcase
end
assign i_dat_s = s_dat_i;
-wire [5:0] req = {m5_cyc_i, m4_cyc_i, m3_cyc_i, m2_cyc_i, m1_cyc_i, m0_cyc_i};
+wire [6:0] req = {m6_cyc_i, m5_cyc_i, m4_cyc_i, m3_cyc_i, m2_cyc_i, m1_cyc_i, m0_cyc_i};
conbus_arb6 arb(
.sys_clk(sys_clk),
Added a 7th master arbitrer
diff --git a/cores/conbus/rtl/conbus_arb6.v b/cores/conbus/rtl/conbus_arb6.v
index d2e6edb..c62a9ba 100644
@@ -19,7 +19,7 @@ module conbus_arb6(
input sys_clk,
input sys_rst,
- input [5:0] req,
+ input [6:0] req,
output [2:0] gnt
);
@@ -45,6 +45,7 @@ always @(*) begin
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[5]) next_state = 3'd5;
+ else if(req[5]) next_state = 3'd6;
end
end
3'd1: begin
@@ -53,6 +54,7 @@ always @(*) begin
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[5]) next_state = 3'd5;
+ else if(req[5]) next_state = 3'd6;
else if(req[0]) next_state = 3'd0;
end
end
@@ -61,6 +63,7 @@ always @(*) begin
if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[5]) next_state = 3'd5;
+ else if(req[5]) next_state = 3'd6;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
end
@@ -69,6 +72,7 @@ always @(*) begin
if(~req[3]) begin
if(req[4]) next_state = 3'd4;
else if(req[5]) next_state = 3'd5;
+ else if(req[5]) next_state = 3'd6;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
@@ -77,6 +81,7 @@ always @(*) begin
3'd4: begin
if(~req[4]) begin
if(req[5]) next_state = 3'd5;
+ else if(req[5]) next_state = 3'd6;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
@@ -85,11 +90,23 @@ always @(*) begin
end
3'd5: begin
if(~req[5]) begin
+ if(req[0]) next_state = 3'd6;
+ else if(req[1]) next_state = 3'd0;
+ else if(req[1]) next_state = 3'd1;
+ else if(req[2]) next_state = 3'd2;
+ else if(req[3]) next_state = 3'd3;
+ else if(req[4]) next_state = 3'd4;
+ end
+ end
+ 3'd6: begin
+
+ if(~req[6]) begin
if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
+ else if(req[4]) next_state = 3'd5;
end
end
endcase
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