This patch adds UART BREAK support. A BREAK signal violates the framing by
transmitting a logical 0 for a period that is at least longer than one
frame.
---
cores/uart/rtl/uart.v | 18 +++++++++++++++---
cores/uart/rtl/uart_transceiver.v | 9 +++++++--
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/cores/uart/rtl/uart.v b/cores/uart/rtl/uart.v
index 3c487df..83a317c 100644
--- a/cores/uart/rtl/uart.v
+++ b/cores/uart/rtl/uart.v
@@ -32,7 +32,9 @@ module uart #(
output tx_irq,
input uart_rx,
- output uart_tx
+ output uart_tx,
+
+ output break
);
reg [15:0] divisor;
@@ -40,7 +42,6 @@ wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
-reg thru;
wire uart_tx_transceiver;
uart_transceiver transceiver(
@@ -57,10 +58,13 @@ uart_transceiver transceiver(
.tx_data(tx_data),
.tx_wr(tx_wr),
- .tx_done(tx_irq)
+ .tx_done(tx_irq),
+
+ .break(break_transceiver)
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
+assign break = break_en & break_transceiver;
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
@@ -70,24 +74,32 @@ assign tx_wr = csr_selected & csr_we & (csr_a[1:0] ==
2'b00);
parameter default_divisor = clk_freq/baud/16;
+reg thru;
+reg break_en;
+
always @(posedge sys_clk) begin
if(sys_rst) begin
divisor <= default_divisor;
csr_do <= 32'd0;
thru <= 1'b0;
+ break_en <= 1'b1;
end else begin
csr_do <= 32'd0;
+ if (break)
+ break_en <= 1'b0;
if(csr_selected) begin
case(csr_a[1:0])
2'b00: csr_do <= rx_data;
2'b01: csr_do <= divisor;
2'b10: csr_do <= thru;
+ 2'b11: csr_do <= break_en;
endcase
if(csr_we) begin
case(csr_a[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= csr_di[15:0];
2'b10: thru <= csr_di[0];
+ 2'b11: break_en <= csr_di[0];
endcase
end
end
diff --git a/cores/uart/rtl/uart_transceiver.v
b/cores/uart/rtl/uart_transceiver.v
index 2348610..dc350bb 100644
--- a/cores/uart/rtl/uart_transceiver.v
+++ b/cores/uart/rtl/uart_transceiver.v
@@ -30,7 +30,9 @@ module uart_transceiver(
input [7:0] tx_data,
input tx_wr,
- output reg tx_done
+ output reg tx_done,
+
+ output reg break
);
//-----------------------------------------------------------------
@@ -77,9 +79,11 @@ always @(posedge sys_clk) begin
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
+ break <= 1'b0;
uart_rx_r <= 1'b0;
end else begin
rx_done <= 1'b0;
+ break <= 1'b0;
if(enable16) begin
uart_rx_r <= uart_rx2;
@@ -103,7 +107,8 @@ always @(posedge sys_clk) begin
if(uart_rx2) begin // stop bit
ok
rx_data <= rx_reg;
rx_done <= 1'b1;
- end // ignore RX error
+ end else if(rx_reg == 8'h00) //
break condition
+ break <= 1'b1;
end else
rx_reg <= {uart_rx2,
rx_reg[7:1]};
end
--
1.7.2.3
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