Hi,
here are some resources for supporting DVI on the M1:
* DVI-A and DDC are already present from VGA. We simply use the same
schematics, with the different connector.
* For DVI-D, we have to use TMDS signaling. It is supported directly by
the FPGA I/Os.
* DVI-A and DVI-D can be combined into one connector (DVI-I)
* DVI-D uses the same signaling as HDMI (without the HDCP crap)
* TMDS is supported in banks 0 and 2 with VCCO=3.3V (Reference document:
http://www.xilinx.com/support/documentation/user_guides/ug381.pdf). On
the M1, there are plenty of suitable I/Os available in bank 2, so we'll
use it. We need a minimum of 8 I/Os (4 differential pairs: RGB + clock).
* Another pin assignment restriction is that differential pairs must
connect to two consecutive pins on the FPGA (labeled P and N).
* According to
http://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf
"use of the low-cost TMDS buffer TMDS141 from Texas Instruments offers
additional signal clean-up and ESD protection up to 6 kV"
* According to
http://rubidium.dyndns.org/pipermail/fpga-synth/2011-April/001667.html
connecting HDMI directly to the FPGA does work correctly. (Thanks
stekern for pointing that out).
* For an alternative ESD protection, we can use varistors like
http://industrial.panasonic.com/ww/news_e/nr200503MC101_e/nr200503MC101_e/366em.pdf
* I prefer the solution without the TI chip and with varistors.
* Schematics of the Atlys devboard with HDMI connections (thanks
stekern):
http://www.digilentinc.com/Data/Products/ATLYS/Atlys_C2_sch.pdf (see
PMODA/JA for the "direct connection" example).
The signals go directly to the FPGA, through 50 ohm series resistors.
There are no pull-ups to 3.3V which are for TMDS _receivers_ only.
* PCB layout guidelines: http://www.pericom.com/pdf/applications/AN204.pdf
http://www.pcb1001.com/2010/04/hdmi-design-guide-for-successful-high.html
It is particularly important to have proper differential transmission
lines, because they are going to be quite long. Bank 2 is on the side of
the BGA opposite to the video connector, and we cannot use bank 0
because it has only one spare I/O left.
Best,
Sébastien
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