On 11/17/2011 10:45 AM, Werner Almesberger wrote:
Of course, all these problems are what a stack that, with my patch, has zero error handling
Do you see errors on the bus?
(and probably still with timing issues left) richly deserves. I'd expect the situation to improve dramatically once ACK generation moves into the SoC.
That's something messy, let's try to avoid it. Hardware CRC with registers that the Navre reads and compares to the values from the packets (instead of computing the CRC in software) is still reasonably possible though.
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