Hi,
On Thursday, December 29, 2011 02:58:03 PM Péteut, Alain (SPACE) wrote:
> Using variables instead of signals prevent insertion of delta time (which
> might boost simulation quite a lot).
Yes, but you have to be careful. Look at this (contrived) example:
process(s_x)
variable tmp: std_logic;
begin
s_a <= tmp;
tmp := s_x;
end process;
What you would expect from this combinatorial process, and what synthesizers
generate, is to permanently drive the value of the signal s_x onto the signal
s_a. The simulation result is quite different: the value of s_a is undefined!
This sort of situation in the generated code can lead to disturbing and
potentially time-sinking simulation/synthesis mismatches.
The Migen FHDL 'combinatorial statement' semantics corresponds to what the
synthesizer produces, i.e. 'connecting a combinatorial circuit between signals
of the design'. This can be achieved by using delta delayed assignments:
signal tmp: std_logic;
process(tmp, s_x)
begin
s_a <= tmp;
tmp <= s_x;
end process;
What happens here is that the simulator runs the process twice (the second
time caused by the event on tmp), and the value of s_a is undefined or
incorrect only for one delta cycle after an event on s_x. This is potentially
inefficient if the simulator does not optimize such code, but it gives the
correct result.
The same situation exists in Verilog if you use blocking assignments.
Sebastien
_______________________________________________
http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
IRC: #milkymist@Freenode
