Thanks for your comments! 

>________________________________
> From: Sebastien Bourdeauducq <[email protected]>
>To: [email protected] 
>Cc: "Péteut, Alain (SPACE)" <[email protected]> 
>Sent: Thursday, December 29, 2011 7:55 PM
>Subject: Re: [Milkymist-devel] VHDL backend test
> 
>Hi, 
>
>On Thursday, December 29, 2011 12:19:43 PM Péteut, Alain (SPACE) wrote:
>> I trying to code a VHDL backend for migen, it's still considered broken for
>> now. Anyway if you'd like to have a look at it:
>> https://github.com/peteut/migen/blob/vhdl/migen/fhdl/vhdl.py
>
>A few comments:
>* I would prefer the generated code to be self-contained, if possible. So you 
>should get rid of the pkg_migen package (which should be easy enough given its 
>current contents).

Agreed.


>* Do not redefine the Constant and Value operator methods. Some of the rest of 
>the code (e.g. optree) calls the _Operator constructor directly, and would not 
>play nice with the VHDL back-end. Instead, translate the operator name when 
>you see a _Operator class, and do not use str() on Constant classes but your 
>own function.

Sure, I was just too lazy for the moment.


>* The VHDL shift operators are broken and should not be used. Use the 
>functions instead (shift_left/shift_right).

Agreed.


>* This is merely a personal preference, but I try to ignore most of VHDL's 
>pesky type system by systematically declaring all my signals as 
>std_logic_vector and using statements like:
>r <= std_logic_vector(to_unsigned(a) + to_unsigned(b));
>when I need arithmetic. They are ugly of course, but they're a lesser evil 
>compared to what VHDL makes you do and think about when you crawl through all 
>the details of the type conversion rules.

I used to use std_logic_vectors for signals as well. 

Rather to call the conversion function I suggest to rely on function 
overloading to keep the code clean.


>
>S.
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