So far, we planned to use 18 pin female headers for the expansion connectors J21 and J22. It turns out that 9*2 female headers are no fun to source. It's possible, but you have to travel deep into China for it.
10*2 would be a considerably more common size. Switching from 18 pin to 20 pin would be a very minor incompatibility to the J21 we have in M1rc2 and M1rc3. Now, what to do with all the new pins ? So far (18 pin headers), the assignment looked like this, beginning with pins 1/2: J21: 2*5V - 2*3V3 - 6*2 signals - 2*GND J22: 3V3+GND - 7*2 signals - 2*GND Since we're already down to just three (one at the moment, but there's some pending cleanup) unused FPGA pins in the 3.3 V domain, I think it wouldn't make much sense to try to use the extra pins for even more signals. Instead, I'd suggest to use them for ground, like this (20 pin headers): J21: 2*GND - 2*5V - 2*3V3 - 6*2 signals - 2*GND J22: 2*GND - 2*3V3 - 7*2 signals - 2*GND Alternatively, we could separate 5V better from the rest, at the cost of increased incompatibility of 5V-using expansion boards and cables with pre-M1r4 units: J21: 2*5V - 2*GND - 2*3V3 - 2*6 signals - 2*GND This is also the configuration shown here: http://downloads.qi-hardware.com/people/adam/m1/tmp/m1r4/FPGA_J21_breakcompatibility.pdf Opinions ? - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
