Hi,
I had a look at the current MMU design. Looks like a good start so far. Some
problems by decreasing importance:
+wire [9:0] dtlb_write_tag;
+wire [9:0] dtlb_read_tag;
===> "Tag" should be renamed "valid" (or something similar), made 1-bit wide
and merged into the "data" memory.
+// CSR Write
+always @(posedge clk_i)
+begin
+ if (csr_write_enable)
+ begin
+ case (csr)
===> This should have a reset.
+assign dtlb_write_tag = (dtlb_flushing == `TRUE)
+ ? `LM32_DTLB_INVALID_TAG
+ : {dtlb_update_vaddr_csr_reg[30:22], `TRUE}; // 10-1
top VA
bits
===> Do not use hardcoded indices (30:22) but macros/params instead to be
consistent with the rest of the code.
else
begin
// Set flag when bus error is detected
- if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
+ if (((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)))
data_bus_error_seen <= `TRUE;
// Clear flag when exception is taken
if ((exception_m == `TRUE) && (kill_m == `FALSE))
===> Extra parentheses do nothing
refilling,
- load_data
+ load_data,
+ // To pipeline
+ dtlb_miss,
+ kernel_mode,
+ pa,
+ csr_read_data
);
===> fix indentation of // To pipeline
S.
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