-----BEGIN PGP SIGNED MESSAGE----- Hash: RIPEMD160 Hi, I'm looking into using the Navré. On the OpenCores page, it says that "All Classic Core instructions implemented, except conditional branches on I/O registers". However, in the source code I see this comment: "/* SBIC, SBIS, SBI, CBI are not implemented */". While SBIC and SBIS are conditional branches on I/O registers, SBI and CBI are not: they're single-instruction read-modify-writes. So, are these instructions implemented or not? From looking through the code I can't see anywhere where they're implemented, but this is my first try reading Verilog (normally I write VHDL) so I may have missed something.
Thanks! Chris -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (GNU/Linux) iEYEAREDAAYFAk+wTvYACgkQXUF6hOTGP7dKbgCfXptzac2NBugBNil2il2OCM5S iokAn3cbPRgT/aeTPa2+mV3kTjC6Eeqo =fvP9 -----END PGP SIGNATURE----- _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
