def gen_list(n):
s = [Signal() for i in range(n)]
return s
def gen_2list(n):
s = [Signal(BV(2)) for i in range(n)]
return s
class Foo:
def __init__(self):
la = gen_list(3)
lb = gen_2list(2)
self.sigs = la + lb
class Bar:
def __init__(self):
self.sigs = gen_list(2)
a = [Bar() for x in range(3)]
b = [Foo() for x in range(3)]
c = b
b = [Bar() for x in range(2)]
output = Signal()
===> old signal namer
reg foo0_la___main__;
reg [1:0] foo0_lb___main__;
reg [1:0] foo0_lb___main___1;
reg foo1_la___main__;
reg foo0_la___main___1;
reg bar3_sigs___main__;
reg bar4_sigs___main__;
reg bar4_sigs___main___1;
wire output;
reg bar0_sigs___main__;
reg bar1_sigs___main__;
reg bar1_sigs___main___1;
reg bar2_sigs___main__;
reg bar2_sigs___main___1;
reg bar0_sigs___main___1;
reg foo1_la___main___1;
reg foo1_la___main___2;
reg [1:0] foo1_lb___main__;
reg bar3_sigs___main___1;
reg [1:0] foo1_lb___main___1;
reg foo2_la___main__;
reg foo2_la___main___1;
reg foo2_la___main___2;
reg [1:0] foo2_lb___main__;
reg [1:0] foo2_lb___main___1;
reg foo0_la___main___2;
===> new signal namer
reg a_bar0_s0;
reg a_bar0_s1;
reg a_bar1_s0;
reg a_bar1_s1;
reg a_bar2_s0;
reg a_bar2_s1;
reg b_foo0_la_s0;
reg b_foo0_la_s1;
reg b_foo0_la_s2;
reg [1:0] b_foo0_lb_s0;
reg [1:0] b_foo0_lb_s1;
reg b_foo1_la_s0;
reg b_foo1_la_s1;
reg b_foo1_la_s2;
reg [1:0] b_foo1_lb_s0;
reg [1:0] b_foo1_lb_s1;
reg b_foo2_la_s0;
reg b_foo2_la_s1;
reg b_foo2_la_s2;
reg [1:0] b_foo2_lb_s0;
reg [1:0] b_foo2_lb_s1;
reg b_bar0_s0;
reg b_bar0_s1;
reg b_bar1_s0;
reg b_bar1_s1;
wire output;
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