Signed-off-by: Michael Walle <mich...@walle.cc>
---
cores/lm32/test/tb_lm32.v | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/cores/lm32/test/tb_lm32.v b/cores/lm32/test/tb_lm32.v
index 0830c88..7007017 100644
--- a/cores/lm32/test/tb_lm32.v
+++ b/cores/lm32/test/tb_lm32.v
@@ -187,7 +187,7 @@ assign dmem_adr = d_adr[15:2];
assign dmem_we = {4{d_cyc & d_stb & d_we}} & d_sel;
// interrupts
-initial interrupt = 32'b0;
+initial interrupt <= 32'b0;
// simulation end request
always @(posedge sys_clk) begin
--
1.7.2.5
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