cores/softusb/rtl/softusb_navre.v | 140 +++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 70 deletions(-) diff --git a/cores/softusb/rtl/softusb_navre.v b/cores/softusb/rtl/softusb_navre.v index d570572..126c6dd 100644 --- a/cores/softusb/rtl/softusb_navre.v +++ b/cores/softusb/rtl/softusb_navre.v @@ -82,9 +82,9 @@ end /* I/O mapped registers */ -parameter IO_SEL_EXT = 2'd0; -parameter IO_SEL_STACK = 2'd1; -parameter IO_SEL_SREG = 2'd2; +localparam IO_SEL_EXT = 2'd0; +localparam IO_SEL_STACK = 2'd1; +localparam IO_SEL_SREG = 2'd2; reg [1:0] io_sel; always @(posedge clk) begin @@ -121,7 +121,6 @@ wire [7:0] GPR_Rr8 = GPR[Rr]; reg [7:0] GPR_Rd; always @(*) begin case(Rd) - default: GPR_Rd = GPR_Rd8; 5'd24: GPR_Rd = U[7:0]; 5'd25: GPR_Rd = U[15:8]; 5'd26: GPR_Rd = pX[7:0]; @@ -130,12 +129,12 @@ always @(*) begin 5'd29: GPR_Rd = pY[15:8]; 5'd30: GPR_Rd = pZ[7:0]; 5'd31: GPR_Rd = pZ[15:8]; + default: GPR_Rd = GPR_Rd8; endcase end reg [7:0] GPR_Rr; always @(*) begin case(Rr) - default: GPR_Rr = GPR_Rr8; 5'd24: GPR_Rr = U[7:0]; 5'd25: GPR_Rr = U[15:8]; 5'd26: GPR_Rr = pX[7:0]; @@ -144,6 +143,7 @@ always @(*) begin 5'd29: GPR_Rr = pY[15:8]; 5'd30: GPR_Rr = pZ[7:0]; 5'd31: GPR_Rr = pZ[15:8]; + default: GPR_Rr = GPR_Rr8; endcase end wire GPR_Rd_b = GPR_Rd[b]; @@ -173,21 +173,20 @@ end reg [3:0] pc_sel; -parameter PC_SEL_NOP = 4'd0; -parameter PC_SEL_INC = 4'd1; -parameter PC_SEL_KL = 4'd2; -parameter PC_SEL_KS = 4'd3; -parameter PC_SEL_DMEML = 4'd4; -parameter PC_SEL_DMEMH = 4'd6; -parameter PC_SEL_DEC = 4'd7; -parameter PC_SEL_Z = 4'd8; -parameter PC_SEL_EX = 4'd9; +localparam PC_SEL_NOP = 4'd0; +localparam PC_SEL_INC = 4'd1; +localparam PC_SEL_KL = 4'd2; +localparam PC_SEL_KS = 4'd3; +localparam PC_SEL_DMEML = 4'd4; +localparam PC_SEL_DMEMH = 4'd6; +localparam PC_SEL_DEC = 4'd7; +localparam PC_SEL_Z = 4'd8; +localparam PC_SEL_EX = 4'd9; /* Exceptions */ reg [7:0] next_irq_ack; always @(*) begin - next_irq_ack = 8'b0; casex(irq) 8'bxxxx_xxx1: next_irq_ack = 8'b0000_0001; 8'bxxxx_xx10: next_irq_ack = 8'b0000_0010; @@ -197,6 +196,7 @@ always @(*) begin 8'bxx10_0000: next_irq_ack = 8'b0010_0000; 8'bx100_0000: next_irq_ack = 8'b0100_0000; 8'b1000_0000: next_irq_ack = 8'b1000_0000; + default: next_irq_ack = 8'b0; endcase end @@ -215,7 +215,6 @@ end reg [3:0] PC_ex; always @(*) begin - PC_ex = 4'b0; casex(irq) 8'bxxxx_xxx1: PC_ex = 4'h0; 8'bxxxx_xx10: PC_ex = 4'h1; @@ -225,6 +224,7 @@ always @(*) begin 8'bxx10_0000: PC_ex = 4'h5; 8'bx100_0000: PC_ex = 4'h6; 8'b1000_0000: PC_ex = 4'h7; + default: PC_ex = 4'h0; endcase end @@ -274,20 +274,20 @@ assign pmem_a = rst ? /* Load/store operations */ reg [3:0] dmem_sel; -parameter DMEM_SEL_UNDEFINED = 3'bxxx; -parameter DMEM_SEL_X = 4'd0; -parameter DMEM_SEL_XPLUS = 4'd1; -parameter DMEM_SEL_XMINUS = 4'd2; -parameter DMEM_SEL_YPLUS = 4'd3; -parameter DMEM_SEL_YMINUS = 4'd4; -parameter DMEM_SEL_YQ = 4'd5; -parameter DMEM_SEL_ZPLUS = 4'd6; -parameter DMEM_SEL_ZMINUS = 4'd7; -parameter DMEM_SEL_ZQ = 4'd8; -parameter DMEM_SEL_SP_R = 4'd9; -parameter DMEM_SEL_SP_PCL = 4'd10; -parameter DMEM_SEL_SP_PCH = 4'd11; -parameter DMEM_SEL_PMEM = 4'd12; +localparam DMEM_SEL_UNDEFINED = 3'bxxx; +localparam DMEM_SEL_X = 4'd0; +localparam DMEM_SEL_XPLUS = 4'd1; +localparam DMEM_SEL_XMINUS = 4'd2; +localparam DMEM_SEL_YPLUS = 4'd3; +localparam DMEM_SEL_YMINUS = 4'd4; +localparam DMEM_SEL_YQ = 4'd5; +localparam DMEM_SEL_ZPLUS = 4'd6; +localparam DMEM_SEL_ZMINUS = 4'd7; +localparam DMEM_SEL_ZQ = 4'd8; +localparam DMEM_SEL_SP_R = 4'd9; +localparam DMEM_SEL_SP_PCL = 4'd10; +localparam DMEM_SEL_SP_PCH = 4'd11; +localparam DMEM_SEL_PMEM = 4'd12; /* ALU */ @@ -678,24 +678,24 @@ end reg [4:0] state; reg [4:0] next_state; -parameter NORMAL = 5'd0; -parameter RCALL = 5'd1; -parameter ICALL = 5'd2; -parameter STALL = 5'd3; -parameter RET1 = 5'd4; -parameter RET2 = 5'd5; -parameter RET3 = 5'd6; -parameter LPM = 5'd7; -parameter STS = 5'd8; -parameter LDS1 = 5'd9; -parameter LDS2 = 5'd10; -parameter SKIP = 5'd11; -parameter WRITEBACK = 5'd12; -parameter EXCEPTION = 5'd13; -parameter RETI1 = 5'd14; -parameter RETI2 = 5'd15; -parameter RETI3 = 5'd16; -parameter RETI4 = 5'd17; +localparam NORMAL = 5'd0; +localparam RCALL = 5'd1; +localparam ICALL = 5'd2; +localparam STALL = 5'd3; +localparam RET1 = 5'd4; +localparam RET2 = 5'd5; +localparam RET3 = 5'd6; +localparam LPM = 5'd7; +localparam STS = 5'd8; +localparam LDS1 = 5'd9; +localparam LDS2 = 5'd10; +localparam SKIP = 5'd11; +localparam WRITEBACK = 5'd12; +localparam EXCEPTION = 5'd13; +localparam RETI1 = 5'd14; +localparam RETI2 = 5'd15; +localparam RETI3 = 5'd16; +localparam RETI4 = 5'd17; always @(posedge clk) begin if(rst) @@ -803,6 +803,7 @@ always @(*) begin 5'b1_0001: dmem_sel = DMEM_SEL_ZPLUS; 5'b1_0010: dmem_sel = DMEM_SEL_ZMINUS; 5'b0_0xxx: dmem_sel = DMEM_SEL_ZQ; + default: dmem_sel = DMEM_SEL_SP_PCL; endcase if(pmem_d[9]) begin /* ST */ @@ -825,32 +826,31 @@ always @(*) begin pc_sel = PC_SEL_INC; pmem_ce = 1'b1; end - 16'b1001_00xx_xxxx_xxxx: begin - if(pmem_d[3:0] == 4'hf) begin - if(pmem_d[9]) begin - /* PUSH */ - push = 1'b1; - dmem_sel = DMEM_SEL_SP_R; - dmem_we = 1'b1; - pc_sel = PC_SEL_INC; - pmem_ce = 1'b1; - end else begin - /* POP */ - pop = 1'b1; - dmem_sel = DMEM_SEL_SP_R; - next_state = WRITEBACK; - end - end else if(pmem_d[3:0] == 4'h0) begin + 16'b1001_00xx_xxxx_1111: begin + if(pmem_d[9]) begin + /* PUSH */ + push = 1'b1; + dmem_sel = DMEM_SEL_SP_R; + dmem_we = 1'b1; pc_sel = PC_SEL_INC; pmem_ce = 1'b1; - if(pmem_d[9]) - /* STS */ - next_state = STS; - else - /* LDS */ - next_state = LDS1; + end else begin + /* POP */ + pop = 1'b1; + dmem_sel = DMEM_SEL_SP_R; + next_state = WRITEBACK; end end + 16'b1001_00xx_xxxx_0000: begin + pc_sel = PC_SEL_INC; + pmem_ce = 1'b1; + if(pmem_d[9]) + /* STS */ + next_state = STS; + else + /* LDS */ + next_state = LDS1; + end 16'b1001_0101_000x_1000: begin /* RET / RETI */ dmem_sel = DMEM_SEL_SP_PCH;