I don't think you will be able to reduce read latency on the M1 with that technique:
By adjusting the bitslip and the DDR Clk Phase, you will probably be able to gain 1 clk4x_rd maximum, but since you still have to align the data to the sys_clk, you will loose all the benefit. Bitslip documentation on Spartan6 is very obscure on Spartan6: http://forums.xilinx.com/t5/Spartan-Family-FPGAs/understanding-BITSLIP-one-more-time/td-p/105327 I'm not sure if it's a true barrel shifter on Spartan6, or as on kintex7: *"Although the repeating pattern seems to show that bitslip is a barrel shifting operation, * *this is not the case. A bitslip operation adds one bit to the input data stream and loses the * *nth bit in the input data stream. This causes the operation on repetitive patterns to appear * *like a barrel shifter operation."* Florent
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