Okay, I installed iverilog. I got this far with the test directory compilation, iverilog compiled but the sim fails...
make iverilog -I. -I../rtl -o tb_lm32_system tb_lm32_system.v lm32_config.v ../rtl/lm32_adder.v ../rtl/lm32_addsub.v ../rtl/lm32_cpu.v ../rtl/lm32_dcache.v ../rtl/lm32_debug.v ../rtl/lm32_decoder.v ../rtl/lm32_dp_ram.v ../rtl/lm32_icache.v ../rtl/lm32_instruction_unit.v ../rtl/lm32_interrupt.v ../rtl/lm32_jtag.v ../rtl/lm32_load_store_unit.v ../rtl/lm32_logic_op.v ../rtl/lm32_mc_arithmetic.v ../rtl/lm32_multiplier.v ../rtl/lm32_ram.v ../rtl/lm32_shifter.v ../rtl/lm32_itlb.v ../rtl/lm32_dtlb.v ../rtl/lm32_top.v ssheikh@GS66-MSAGPC3 /cygdrive/c/GMSAG/CPU_TESTING/lm32-master/test $ make sim_% lm32-elf-gcc -Tlinker.ld -fno-builtin -nostdlib -lgcc -o %.elf /cygdrive/c/lscc/diamond/2.2_x64/micosystem/gtools/lm32/bin/../lib/gcc/lm32-elf/4.3.0/../../../../lm32-elf/bin/ld: warning: cannot find entry symbol _start; defaulting to 00000000 lm32-elf-objcopy -O verilog %.elf %.vh lm32-elf-objcopy: %.vh: Invalid bfd target Makefile:43: recipe for target '%.vh' failed make: *** [%.vh] Error 1 rm %.elf On Fri, Jan 10, 2014 at 9:10 AM, Sébastien Bourdeauducq < [email protected]> wrote: > On 01/10/2014 03:13 PM, Salman Sheikh wrote: > > Okay, I got that compiled but I am not able to get the simulation > > running on modelsim. I need to change the Makefile (or better yet > > understand what vvp equivalent is for Modelsim).... > > What exactly do you need Modelsim for? If it's for speed, you may want > to try Verilator, which is free and very fast - sometimes faster than > Modelsim. If you do, please share your testbenches/compilation scripts. > > Sébastien > > _______________________________________________ > Devel mailing list > [email protected] > https://ssl.serverraum.org/lists/listinfo/devel > -- Even a Smile is charity :) - Prophet Muhammad
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