Rolf, We have identified a need in certain high performance applications to specify memory sections -> L3 -> L2 - >L1 -> specific core -> specific CPU -> specific machine. These tend toward hybridized CUDA apps where other sections of the CPU are involved in non-CUDA (non-GPU) functions. In our discussions, however, we haven't come across others who see the same need. IOW, we are a very small market.
Ken On Mon, 2011-05-16 at 14:52 -0700, Rolf vandeVaart wrote: > I see in the sm BTL that there is the concept of memory affinity and > the potential to support multiple memory pools. I am curious if > anyone is making use of that feature? I am looking in the function > sm_btl_first_time_init() in the btl_sm.c file. > > > > Thanks, > > Rolf > > > > > > ______________________________________________________________________ > This email message is for the sole use of the intended recipient(s) > and may contain confidential information. Any unauthorized review, > use, disclosure or distribution is prohibited. If you are not the > intended recipient, please contact the sender by reply email and > destroy all copies of the original message. > > ______________________________________________________________________ > > _______________________________________________ > devel mailing list > de...@open-mpi.org > http://www.open-mpi.org/mailman/listinfo.cgi/devel ===================== Kenneth A. Lloyd CEO - Director of Systems Science Watt Systems Technologies Inc. www.wattsys.com kenneth.ll...@wattsys.com This e-mail is covered by the Electronic Communications Privacy Act, 18 U.S.C. 2510-2521 and is intended only for the addressee named above. It may contain privileged or confidential information. If you are not the addressee you must not copy, distribute, disclose or use any of the information in it. If you have received it in error please delete it and immediately notify the sender.
