I've run this hg tree with the intel, IBM, and IMB suites on a Romley server 
with 20 cores for NP values of 2,3,4,...,19,20.  The only failures were the IBM 
spawn tests (which are expected, because I ran with "--mca btl sm,self").

So -- +1 on this from me (disclaimer: I haven't looked at the code).


On Aug 5, 2012, at 6:38 AM, Gutierrez, Samuel K wrote:

> WHAT:
> 
> The majority of the code required to get away from explicit RML usage during
> shared memory initialization is complete. With this update, the sm BTL and sm
> mpool modex around the information required for setup.
> 
> I've completed some initial testing and everything seems to be working
> properly, but additional testing and feedback is greatly appreciated -- and
> almost certainly required.
> 
> Things that haven't been tested:
> o The sm BTL with progress threads enabled (OMPI_ENABLE_PROGRESS_THREADS).
> o The sm BTL with any kernel assistance enabled.
> 
> WHY: In preparation for the eventual BTL move.
> 
> WHERE: 
> M       opal/mca/shmem/posix/shmem_posix_module.c
> M       opal/mca/shmem/sysv/shmem_sysv_module.c
> M       opal/mca/shmem/mmap/shmem_mmap_module.c
> M       opal/mca/shmem/windows/shmem_windows_module.c
> M       ompi/mca/btl/sm/btl_sm.c
> M       ompi/mca/btl/sm/btl_sm_component.c
> M       ompi/mca/btl/sm/help-mpi-btl-sm.txt
> M       ompi/mca/btl/sm/btl_sm.h
> M       ompi/mca/btl/sm/btl_sm_fifo.h
> M       ompi/mca/mpool/sm/mpool_sm_component.c
> M       ompi/mca/mpool/sm/mpool_sm.h
> M       ompi/mca/common/sm/common_sm.c
> M       ompi/mca/common/sm/common_sm.h
> 
> The majority of changes that most will care about are in btl/sm/* and 
> mpool/sm/*
> 
> The branch can be found:
> https://bitbucket.org/samuelkgutierrez/rmllesssm
> 
> TIMEOUT: If everything looks okay, Aug 10, 2012. If not, some time after 
> issues
> have been resolved.
> 
> Thanks,
> 
> Sam
> 
> _______________________________________________
> devel mailing list
> de...@open-mpi.org
> http://www.open-mpi.org/mailman/listinfo.cgi/devel


-- 
Jeff Squyres
jsquy...@cisco.com
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