Author: Razvan Crainea <raz...@opensips.org>
Date: 2016-09-19 (Mon, 19 Sep 2016)
usrloc: fix race between update for different registers
In case there are two REGISTER messages with incremental CSEQ are
replicated in a different order, skip the processing, since this has
already been resolved by the master instance.
Thanks to Deniz Beskök for reporing this
Devel mailing list