The commit is pushed to "branch-rh7-3.10.0-514.26.1.vz7.35.x-ovz" and will 
appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-514.26.1.vz7.33.22
------>
commit 3fc24d5c90ee96abf500a58fdfce05eb0ebdcb30
Author: Radim Krčmář <rkrc...@redhat.com>
Date:   Mon Aug 7 14:41:10 2017 +0400

    ms/KVM: x86: save one bit in ctxt->d
    
    Alignments are exclusive, so 5 modes can be expressed in 3 bits.
    
    Signed-off-by: Radim Krčmář <rkrc...@redhat.com>
    Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
    
    https://jira.sw.ru/browse/PSBM-69206
    ms commit: 48520187894324ac50b323c140096cd6d5c96614
    
    Signed-off-by: Evgeny Yakovlev <eyakov...@virtuozzo.com>
---
 arch/x86/kvm/emulate.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index aeb96c4..e9be9e9 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -159,9 +159,11 @@
 #define Src2GS      (OpGS << Src2Shift)
 #define Src2Mask    (OpMask << Src2Shift)
 #define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
+#define AlignMask   ((u64)7 << 41)
 #define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
-#define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
-#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
+#define Unaligned   ((u64)2 << 41)  /* Explicitly unaligned (e.g. MOVDQU) */
+#define Avx         ((u64)3 << 41)  /* Advanced Vector Extensions */
+#define Aligned16   ((u64)4 << 41)  /* Aligned to 16 byte boundary (e.g. 
FXSAVE) */
 #define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
 #define NoWrite     ((u64)1 << 45)  /* No writeback */
 #define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
@@ -172,7 +174,6 @@
 #define NearBranch  ((u64)1 << 52)  /* Near branches */
 #define No16       ((u64)1 << 53)  /* No 16 bit operand */
 #define IncSP       ((u64)1 << 54)  /* SP is incremented before ModRM calc */
-#define Aligned16   ((u64)1 << 55)  /* Aligned to 16 byte boundary (e.g. 
FXSAVE) */
 
 #define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
 
@@ -658,19 +659,21 @@ static void set_segment_selector(struct x86_emulate_ctxt 
*ctxt, u16 selector,
  */
 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
 {
+       u64 alignment = ctxt->d & AlignMask;
+
        if (likely(size < 16))
                return 1;
 
-       if (ctxt->d & Aligned)
-               return size;
-       else if (ctxt->d & Unaligned)
-               return 1;
-       else if (ctxt->d & Avx)
+       switch (alignment) {
+       case Unaligned:
+       case Avx:
                return 1;
-       else if (ctxt->d & Aligned16)
+       case Aligned16:
                return 16;
-       else
+       case Aligned:
+       default:
                return size;
+       }
 }
 
 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
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