The CFSR numbers indicate that the stacked PC was invalid upon return from
ISR. Is the stack of the sleeping process being corrupted somehow?

http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihcfefj.html#Cihgbdbi
(go to UsageFault Status Register)

Do you have the possibility to run your device with a debugger attached?
You should try to look at the differences in the contents of the thread
stack between the two different methods (xtimer vs RTC). Also, check the
values of the core registers before the hardfault, likely near the bx r0 in
isr_svc, (did it run that far?)

Regards,
Joakim

On Fri, Sep 16, 2016 at 4:31 PM, Anon Anonymous <anon1644...@gmail.com>
wrote:

> Hi,
>
> Any ideas on this?
>
> 2016-09-14 22:13 GMT+03:00 Anon Anonymous <anon1644...@gmail.com>:
>
>> Sure. Here it is: http://pastebin.com/ZGwtZKDd
>>
>> 2016-09-14 21:03 GMT+03:00 Joakim Nohlgård <joakim.nohlg...@eistec.se>:
>>
>>> Do you have some example code that you can share which triggers this
>>> fault?
>>>
>>> Best regards, Joakim
>>>
>>> On Sep 14, 2016 7:50 PM, "Anon Anonymous" <anon1644...@gmail.com> wrote:
>>>
>>>> Hello,
>>>>
>>>> I trying to unlock mutex in RTC Alarm ISR and after alarm shoots and
>>>> mutex is unlocked, the thread switch request is pending. RTC ISR in rtc.c
>>>> file check that flag and calls thread_yield() to call a scheduler. After
>>>> PendSV interrupt is triggered, HardFault occurs right after PendSV enabling
>>>> command.
>>>>
>>>> When the same operations done from for example, TIM interrupt which
>>>> used by xtimer, context switching goes well.
>>>>
>>>> FSR/FAR:
>>>>>  CFSR: 0x00040000
>>>>>  HFSR: 0x40000000
>>>>>
>>>>
>>>>
>>>> My device is STM32L151.
>>>>
>>>> Best regards,
>>>> Anon
>>>>
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>>>>
>>>>
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>>>
>>
>
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