Probably true. I could change
rtems_cache_invalidate_entire_instruction_cpu_set(set) to
rtems_cache_invalidate_entire_instruction_all_processors() instead. Or
make the original rtems_cache_invalidate_entire_instruction() notify all
processors when running SMP, but I guess that could be dangerous.
Daniel Cederman
Software Engineer
Aeroflex Gaisler AB
Aeroflex Microelectronic Solutions – HiRel
Kungsgatan 12
SE-411 19 Gothenburg, Sweden
Phone: +46 31 7758665
ceder...@gaisler.com
www.Aeroflex.com/Gaisler
On 2014-07-07 08:53, Sebastian Huber wrote:
I think instruction cache operations scoped by processors make no sense
on SMP. Every processor should have the same view to the instruction
memory.
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