Hello Sebastian and Oleg, On Monday 22 of September 2014 07:35:38 Sebastian Huber wrote: > On 22/09/14 06:36, Мороз Олег wrote: > > Hello everyone. i'm new to BSP development. We have a project > > which is uses some kind of cortex-m0 microcontroller. As i understand > > it's armv6-m family. Is this CPU family is supported by rtems? I'm > > reading the book called "BSP and device driver development guide" and it > > says look at > > "cpukit/score/cpu/CPU". This directory contains only armv7-m and armv4 > > files. Is it correct? > > The armv7-m support will probably work also for a Cortex-M0.
I think that M3 context switch would be mostly OK. Exception and interrupts model is the same as for M3, but I have feeling that there exists option to use some simplified one - but it can be for M1. But you need to use M0 specific GCC options. We use GCC for nRF51 Cortex-M0 with next options arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb --std=gnu99 -Wall -mfloat-abi=soft Else GCC can use Thumb2 instructions which are not supporeted by ARMv6-m. For example Thumb instructions CBZ, CBNZ, IT emitted by GCC for M3 are not supported by M0. So toolchain rebuild is required for sure. Best wishes, Pavel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel